m27481 Mindspeed Technologies, m27481 Datasheet - Page 4

• Manufacturer Part Number: m27481
• Description: 3rd Generation Traffic Stream Processor ?tsp3
• Manufacturer: Mindspeed Technologies

General Information: [phone]
Product Features
Physical Interfaces:
• Two bi-directional “universal link” data-
• DDR SDRAM interface
• Optional glueless interface to
• PCI interface for data & control plane
• I
www.mindspeed.com/salesoffices
4000 MacArthur Blvd., East Tower
- POS-PHY & UTOPIA Level 2, configurable
- 64 independent egress FIFO’s
- Two integrated Ethernet MACs
- 2.6 GB sustained bandwidth, 64 to 256 MB of
- Supporting > 100M searches per second
- Up to 64K table entries
- Rev 2.1-2.3 compliant, 32-bit, up to 66 MHz, 3.3 V
path interfaces – each configurable as:
external CAM
Newport Beach, CA 92660-3007
2
Headquarters – Newport Beach
for 8/16-bit modes, up to 125 MHz
(MII, RMII, GMII, TBI)
64-bit, up to 166 MHz, 2.5V, with ECC
C interface for boot EEPROM
27481-BRF-001-C M04-0914
© 2005 Mindspeed Technologies, Inc. All rights reserved. Mindspeed and the
Mindspeed logo are trademarks of Mindspeed Technologies. All other trademarks are
the property of their respective owners. Although Mindspeed Technologies strives for
accuracy in all its publications, this material may contain errors or omissions and is
subject to change without notice. This material is provided as is and without any
express or implied warranties, including merchantability, fitness for a particular
purpose and non-infringement. Mindspeed Technologies shall not be liable for any
special, indirect, incidental or consequential damages as a result of its use.
Hardware Internals:
Processing Core:
Hardware Co-processing Engines:
• Channel Descriptor Lookup Engine (CDL)
• Context Cache and Data RAM (CCR)
- Single Octave microprocessor core – includes:
- Per flow multi-protocol classification using
- On-chip work area and staging area for all
• 32-bit RISC engine, core frequency of 333 MHz,
internal TCAM, suitable for ATM, MPLS, IP
Diffserv, Ethernet, stacked VLAN tagged
Ethernet frames, etc.
command and data processing events, posting
and prioritization of events for the Octave
processor, contains the DMA engines for moving
data to and from memory and egress
4 stage pipeline, single cycle instruction execu-
tion, 16 K instruction cache, 64 general purpose,
32-bit registers addressable by all instructions
• Traffic Scheduling System (TSS)
• Buffer Management Engine (BME)
- Support for up to 8 buffer classes, dedicated
Device Physicals:
to managing the free buffer memory pools
- Performs rate shaping and scheduling for all
- Voltage levels: 1.2 V, 2.5 V, 3.3 V - Package: 1156
ingress and egress traffic, 64 slot, calendar based
scheduler with dual GCRA conforming shaping per
connection, configurable scoreboards supporting
up to 64 K packet or cell streams on up to 64
ports, non-blocking, traffic shaping of packets
and cells from 64 Kbps to over 2 Gbps speeds,
within 1% accuracy, token bucket port rate
shaping by backpressure or internal clock
PBGA, 35mm x 35mm -Power: 5.5W maximum -
operation temperature: -40ºC to +85ºC