ocx256 ETC-unknow, ocx256 Datasheet - Page 7

• Manufacturer Part Number: ocx256
• Description: Ocx256 Crosspoint Switch
• Manufacturer: ETC-unknow

1. Introduction
Fairchild Semiconductor
The OCX256 is a differential crosspoint-switching device. The main functional block of the device is a Switch
Matrix as shown in Figure 1. The Switch Matrix is a x-y structure supporting an input-to-output data flow.
Figure 2 shows a conceptual view of the switch matrix with inputs connected to the horizontal trace and outputs
to the vertical trace. Connections between vertical and horizontal lines are implemented with a proprietary high-
performance buffering circuit. Signal path delays through the Switch Matrix are very well balanced, resulting in
predictable and uniform pin-to-pin delays.
The Active SRAM cells are responsible for establishing connections in the switch matrix by turning on the
interconnect circuit, while the Loading SRAM cell can be used to store a second configuration that can be
transferred to the Active SRAM cell at a later time. The two SRAM cells are arranged so that a double buffered
scheme can be employed. Through the use of an internal signal (generated automatically during a programming
cycle) it is possible to store a second configuration map in the Loading SRAM while the Active SRAM
maintains its present connection status. When the UPDATE# signal is asserted low (# denotes active low), the
contents of the Loading SRAM cell are transferred to the Active SRAM cell and the switch matrix connection is
either made or broken.
The UPDATE# signal can be used to control when the switch matrix is reconfigured. For instance, as long as the
UPDATE# signal is de-asserted (held high), the Loading SRAM cells for the entire switch matrix could be
changed without affecting the current configuration of the switch. When the UPDATE# signal is asserted low,
the entire switch matrix would be reconfigured simultaneously. If the UPDATE# signal is asserted continuously,
all crosspoint programming commands (generated by RapidConfigure or JTAG programming cycles) will take
effect immediately, since the Loading SRAM cell’s contents will be transferred directly to the Active SRAM
cell.
Note – For the purpose of clarity, the logic diagrams within this datasheet are conceptual
representations only and do not show actual circuit implementation.
Data
Proprietary High-performance
Loading
SRAM
Cell
Buffering Circuit
Figure 2
UPDATE#
SRAM
Active
OCX256 Crosspoint Switch—Advanced Datasheet
Cell
[Rev. 2.0] 3/21/02
OCX256 Switch Matrix
7