bcm5714 Broadcom Corp., bcm5714 Datasheet - Page 2

• Manufacturer Part Number: bcm5714
• Description: Pci Express To Pci-x I/o Bridge With Integrated Dual Gigabit Ethernet Ports
• Manufacturer: Broadcom Corp.

The BCM5714S device is a highly integrated communication and
storage bridge for entry-level servers and embedded applications. The
primary applications are UP and DP servers featuring PCI Express
connectivity for I/O expansion.
The primary features of the BCM5714S are:
• Dual Gigabit NIC ports
• One full 64-bit/133-MHz PCI-X 1.0 bus
• Host interface of PCI Express
• Integrated SerDes
The BCM5714S connects to server chip sets with an x4 PCI Express
interface and provides an independent PCI-X 1.0 bus for peripheral
connectivity. The x4 PCI Express interface is a flexible design and
supports x1 and x2 PCI Express connectivity as well. The PCI-X bus is
64 bits wide and runs at 133 MHz.
As an integrated I/O bridge that provides a high performance data flow
path between the PCI-E host interface and the integrated I/O sub system,
the PCI-X bus provides high-performance I/O expansion within the
system, and the Gigabit Ethernet interfaces provide high performance
network interfaces to the external world. The 64-bit PCI-X bus segment
operates at 33 MHz, 66 MHz, 100 MHz, and 133 MHz. The Gigabit
Ethernet Interface represents Broadcom's fourth generation of server
controllers with fully integrated SerDes transceivers.
Broadcom
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and/or the EU. Any other trademarks or trade names mentioned are the property of their respective
owners.
BROADCOM CORPORATION
16215 Alton Parkway,
Irvine, California 92619-7013
© 2009 by BROADCOM CORPORATION. All rights reserved.
5714S-PB03-R
®
, the pulse logo, Connecting everything
04/06/09
®
®
, and the Connecting everything logo are among
O V E R V I E W
The PCI-X Bridge also has the following features:
• Allows concurrency between the PCI Express and the PCI-X buses
• Eight deep PCI Express-to-PCI-X memory write posting (PCI
• Four deep PCI Express-to-PCI-X non-posted request queue (PCI
• Caching with a 16-deep, 32-byte I/O cache for PCI to main memory
• Support write-through caching protocol
• Supports up to 14 outstanding split transactions (PCI-X-to-main
• Eight-deep PCI-X-to-PCI Express request queue (PCI-X-to-main
• Parity protection on the PCI-X bus in a conventional PCI and PCI-X
• Optional ECC protection on the PCI-X bus in PCI-X mode1
• Three programmable regions each for PCI-X memory, and one
• VGA-compatible addressing support
• Multiple I/O APIC support
• Peer-to-peer transfer support
• Integrated PCI-X bus arbitration that supports up to four PCI-X bus
• PCI-X bus error reporting
• RAS features
Express-to-PCI-X transactions)
Express-to-PCI-X transactions)
transactions for each PCI bus
memory transactions)
memory transactions)
mode1
region for I/O
masters
Phone: [phone]
Fax: [phone]
E-mail: [e-mail]
Web: www.broadcom.com