bcm5714c Broadcom Corp., bcm5714c Datasheet - Page 2

• Manufacturer Part Number: bcm5714c
• Description: Pci Express To-pci-x I/o Bridge With Integrated Dual Gigabit Ethernet Ports
• Manufacturer: Broadcom Corp.

The BCM5714C device is a highly integrated communication and
storage bridge for entry-level servers and embedded applications. The
primary applications of the BCM5714C are UP and DP servers featuring
PCI Express connectivity for I/O expansion.
The BCM5714C provides these key features:
• Dual gigabit NIC ports (MAC and PHY)
• One full 64-bit/133 MHz PCI-X 1.0 bus
• Host interface of PCI Express
The BCM5714C connects to server chip sets with an x4 PCI Express
interface and provides an independent PCI-X 1.0 bus for peripheral
connectivity. The x4 PCI Express interface is a flexible design and
supports x1 and x2 PCI Express connectivity as well. The PCI-X bus is
64 bits wide and runs at 133 MHz.
As an integrated I/O bridge that provides a high-performance data flow
path between the PCI Express host interface and the integrated I/O
subsystem, the PCI-X bus provides high-performance I/O expansion
within the system, while the Gigabit Ethernet interfaces provide high
performance network interfaces to the external world. The 64-bit PCI-X
bus segment operates at 33 MHz, 66 MHz, 100 MHz, and 133 MHz. The
GbE interface represents the fourth generation of Broadcom
controllers with fully integrated copper transceivers.
The features of the PCI-X bridge include the following:
• Allow concurrency between the PCI Express and the PCI-X buses
Broadcom
and Smart Load Balancing™ are among the trademarks of Broadcom Corporation and/or its affiliates in
the United States, certain other countries and/or the EU. Any other trademarks or trade names mentioned
are the property of their respective owners.
BROADCOM CORPORATION
5300 California Avenue
Irvine, California 92617
© 2009 by BROADCOM CORPORATION. All rights reserved.
5714C-PB03-R
®
, the pulse logo, Connecting everything
04/15/09
DDR
DDR
®
®
, the Connecting everything logo, NetXtreme
Processor
Memory Controller
System Block Diagram
Southbridge
®
server
O V E R V I E W
Processor
®
• Eight-deep PCI Express-to-PCI-X memory write posting (PCI
• Four-deep PCI Express-to-PCI-X non-posted request queue (PCI
• Caching with a 16-deep, 32-byte I/O cache for PCI-to-main memory
• Support write-through caching protocol
• Support up to 14 outstanding split transactions (PCI-X-to-main
• Eight-deep PCI-X-to-PCI Express request queue (PCI-X-to-main
• Parity protection on the PCI-X bus in a conventional PCI and PCI-X
• Optional ECC protection on the PCI-X bus in PCI-X mode1
• Three programmable regions each for PCI-X memory and one region
• VGA-compatible addressing support
• Multiple I/O APIC support
• Peer-to-peer transfer support
• Integrated PCI-X bus arbitration that supports up to four PCI-X bus
• PCI-X bus error reporting
• RAS features
,
Express-to-PCI-X transactions)
Express-to-PCI-X transactions)
transactions for each PCI bus
memory transactions)
memory transactions)
mode1
for I/O
masters
Express
PCI
Dual GbE
Phone: [phone]
Fax: [phone]
E-mail: [e-mail]
Web: www.broadcom.com
PCI-X