co561ad-s Connect One Ltd., co561ad-s Datasheet - Page 18

• Manufacturer Part Number: co561ad-s
• Description: The Co561ad-s, Ichip? Internet Controller?, Is Part Of A Family Of Intelligent Peripheral Devices That Provide Internet Connectivity Solutions To A Myriad Of Embedded Devices.
• Manufacturer: Connect One Ltd.

11-3500-00
Signal
-BHE
HOLD
HLDA
-RD
-WR
(*)Note: Currently the local BUS is not in use in the CO561AD-S.
iChip CO561AD-S Datasheet
Type
O
O
O
O
I
Pin no.
31
62
61
68
52
BUS HIGH Enable: This pin and the least-significant
address bit (AD0 or A0) indicate to the system, which
bytes of the data BUS (upper, lower, or both) participate
in a BUS cycle. The ~BHE and A0 pins are encoded as
shown in the table below.
During a BUS hold or reset condition, -BHE is in a
HIGH-impedance state.
This pin should be left Not Connected.
BUS Hold Request: when HOLD is HIGH, it indicates
that an external BUS master needs control of the local
BUS.
This pin should be connected to GND.
BUS Hold Acknowledge: This pin goes HIGH to
indicate to an external BUS master that the iChip has
released control of the local BUS.
This pin should be left Not Connected.
READ: This pin indicates that the iChip is performing a
memory read cycle. -RD floats during a BUS hold
condition.
This pin should be left Not Connected.
WRITE: This pin indicates that the iChip is performing
a memory write cycle. -WR floats during a BUS hold
condition.
This pin should be left Not Connected.
~BHE AD0
0
1
0
1
0
0
1
1
Type of BUS cycle
Word Transfer
Even Byte Transfer
Odd Byte Transfer
N/A
Description
Pin Descriptions
5-3