emc2103-3-kp-tr Standard Microsystems Corp., emc2103-3-kp-tr Datasheet - Page 53
emc2103-3-kp-tr
Manufacturer Part Number
emc2103-3-kp-tr
Description
Emc2103 Rpm-based Fan Controller With Hardware Thermal Shutdown
Manufacturer
Standard Microsystems Corp.
Datasheet
1.EMC2103-3-KP-TR.pdf
(85 pages)
- Current page: 53 of 85
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RPM-Based Fan Controller with HW Thermal Shutdown
Datasheet
SMSC EMC2103
6.17
6.18
ADDR
ADDR
2Bh
2Ah
R/W
R/W
R/W
R/W
The Fan Interrupt Enable Register controls the masking for errors generated by the Fan Driver. When
a channel is masked, it will not cause the ALERT pin to be asserted when an error condition is
detected.
Bit 1 - SPIN_INT_EN - Allows the FAN_SPIN bit to assert the ALERT pin.
Bit 0 - STALL_INT_EN - Allows the FAN_STALL bit or DRIVE_FAIL bit to assert the ALERT pin.
The PWM Config Register controls the output type and polarity of the PWM output.
Bit 4 - PWM_OT - Determines the output type for the PWM pin.
Bit 0 - POLARITY1 - Determines the polarity of PWM1 (if enabled).
The PWM Base Frequency Register controls base frequency of the PWM output.
Bits 1-0 - PWM_BASE[1:0] - Determines the base frequency of the PWM driver (PWM).
PWM Configuration Register
PWM Base Frequency Register
‘0’ (default) - the FAN_SPIN bit will not assert the ALERT pin though it will still update the Status
Register normally.
‘1’ - the FAN_SPIN bit will assert the ALERT pin.
‘0’ (default) - the FAN_STALL bit or DRIVE_FAIL bit will not assert the ALERT pin though will still
update the Status Register normally.
‘1’ - the FAN_STALL bit will assert the ALERT pin.
‘0’ (default) - The PWM pin is configured as an open drain output.
‘1’ - The PWM pin is configured as a push-pull output.
‘0’ (default) - the Polarity of the PWM driver is normal. A drive setting of 00h will cause the output
to be set at 0% duty cycle and a drive setting of FFh will cause the output to be set at 100% duty
cycle.
‘1’ - The Polarity of the PWM driver is inverted. A drive setting of 00h will cause the output to be
set at 100% duty cycle and a drive setting of FFh will cause the output to be set at 0% duty cycle.
REGISTER
REGISTER
PWM Base
Frequency
Config
PWM
Table 6.25 PWM Base Frequency Register
B7
B7
Table 6.24 PWM Configuration Register
-
-
B6
B6
-
-
DATASHEET
B5
B5
-
-
53
PWM_
B4
-
OT
B4
B3
-
B3
-
B2
-
B2
-
PWM_BASE[1:0
B1
B1
-
]
Revision 0.88 (06-30-08)
POLA
RITY
B0
B0
DEFAULT
DEFAULT
03h
00h
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