hi-8589pqt Holt Integrated Circuits, Inc., hi-8589pqt Datasheet - Page 5

• Manufacturer Part Number: hi-8589pqt
• Description: Transmitter With Line Driver And Dual Receivers
• Manufacturer: Holt Integrated Circuits, Inc.

FUNCTIONAL DESCRIPTION (cont.)
TRANSMITTER
A block diagram of the transmitter section is shown in Figure 3.
FIFO OPERATION
The FIFO is loaded sequentially by first pulsing
and then
the 31 bit word in the next available position of the FIFO. If TX/R,
the transmitter ready flag is high (FIFO empty), then 8 words,
each 31 bits long, may be loaded. If TX/R is low, then only the
available positions may be loaded. If all 8 positions are full, the
FIFO ignores further attempts to load data.
DATA TRANSMISSION
When ENTX goes high, enabling transmission, the FIFO
positions are incremented with the top register loading into the
data transmission shift register. Within 2.5 data clocks the first
data bit appears at either TXA(OUT) or TXB(OUT). The 31 bits in
the data transmission shift register are presented sequentially to
the outputs in the ARINC 429 format with the following timing:
The word counter detects when all loaded positions are
transmitted and sets the transmitter ready flag, TX/R, high.
ARINC DATA BIT TIME
WORD GAP TIME
PL2
NULL BIT TIME
DATA BIT TIME
to load byte 2. The control logic automatically loads
FIGURE 3.
LOAD SHIFT REGISTER
31 BIT PARALLEL
8 X 31 FIFO
DATA BUS
TRANSMITTER BLOCK DIAGRAM
HIGH SPEED
10 Clocks
40 Clocks
5 Clocks
5 Clocks
PL1
LOW SPEED
HOLT INTEGRATED CIRCUITS
320 Clocks
80 Clocks
40 Clocks
40 Clocks
to load byte 1
LOAD
BIT CLOCK
ADDRESS
HI-8581, HI-8589
WORD CLOCK
GENERATOR
5
BIT BD12
TRANSMITTER PARITY
The parity generator counts the ONES in the 31-bit word. If the
BD12 control word bit is set low, the 32nd bit transmitted will
make parity odd. If the control bit is high, the parity is even.
SELF TEST
If the BD05 control word bit is set low, the digital outputs of the
transmitter are internally connected to the logic inputs of the
receivers, bypassing the analog bus interface circuitry. Data to
Receiver 1 is as transmitted and data to Receiver 2 is the
complement. All data transmitted during self test is also present
on the TXA(OUT) and TXB(OUT) line driver outputs.
SYSTEM OPERATION
The two receivers are independent of the transmitter. Therefore,
control of data exchanges is strictly at the option of the user. The
only restrictions are:
PARITY
within one ARINC word cycle.
Both bytes must be retrieved to clear the data ready flag.
low until TX/R, transmitter ready flag, goes high. Otherwise,
one ARINC word is lost during transmission.
1. The received data may be overwritten if not retrieved
2. The FIFO can store 8 words maximum and ignores
attempts to load addition data if full.
3. Byte 1 of the transmitter data must be loaded first.
4. Either byte of the received data may be retrieved first.
5. After ENTX, transmission enable, goes high it cannot go
CLOCK
DATA
SEQUENCER
NULL TIMER
DATA AND
WORD COUNTER
FIFO CONTROL
DATA CLOCK
SEQUENCER
CONTROL BIT
WORD GAP
COUNTER
LOADING
DIVIDER
AND
FIFO
AND
BD13
BIT
SEQUENCE
WORD COUNT
INCREMENT
START
LINE DRIVER
TXA(OUT)
TXB(OUT)
TX CLK
CLK
TX/R
ENTX
PL1
PL2