s3485 Applied Micro Circuits Corporation (AMCC), s3485 Datasheet

s3485

Manufacturer Part Number

s3485

Description

Sonet/sdh/fec/fc/ge/hdtv/dtv/d1/escon Multirate 4-bit Transceiver

Manufacturer

Applied Micro Circuits Corporation (AMCC)

Datasheet

1.S3485.pdf (2 pages)

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S3485

SONET/SDH/FEC/FC/GE/HDTV/DTV/D1/ESCON Multirate 4-bit Transceiver

Features

• Operational from 2.00 Gbps to 3.00 Gbps

• Supports:

• Low Power (300 mW Typical)

• Built-In Self Test (BIST) Feature

• 121 pin PBGA package with Green/RoHS com-

• On-chip High-Frequency PLL for Clock Genera-

• 4-bit LVDS Parallel Data Path

• TX and RX Lock Detect Indication

• Serial Loop Timing Mode

• Line and Diagnostic Loopback Mode for Faulty

• Operational Temperature Range Up to 85°C

• Dual 1.2 V and 1.8 V supply

• Complies with OIF SFI-4/Telecordia/ITU-T

Transmitter Features

• Reference frequency of 155.52 MHz (or equiv-

• 155.52 MHz (or equivalent rate) clock output

• Internal, self-initializing FIFO to decouple

Receiver Features

• Recovers clock from 2.00 to 3.00 Gbps

• Low-jitter CML differential or single-ended

• Reference frequency of 155.52 MHz (or equiv-

Applications

• SONET/SDH-based transmission systems

• SONET/SDH modules

• Wavelength Division Multiplexing (WDM)

• Section repeaters

• Add Drop Multiplexers (ADM)

• Broad-band cross-connects

• Fiber Optic Terminators

• Fiber Optic Test Equipment

• OC-48 with or w/o FEC

• OC-24 with or w/o FEC

• OC-12 with or w/o FEC

• OC-3 with or w/o FEC

• HDTV (1.485 Gbps)

• D1 (1.38 Gbps)

• Fibre Channel (1062 Mbps)

• 2 x Fibre Channel (2.124 Gbps)

• Gigabit Ethernet (1.25 Gbps)

• DTV (143.18 Mbps)

• ESCON (200 Mbps)

pliant lead free option

tion and Clock Recovery

Node Identification

Specifications

alent rate)

transmit clocks

serial interface

alent rate)

Description

The S3485 SONET/SDH transceiver chip is a fully

integrated serialization/deserialization SONET

multi-rate interface device. The S3485 receives a

scrambled Non-Return-to-Zero (NRZ) signal and

recovers the clock from the data. The chip

performs all necessary serial-to-parallel and

parallel-to-serial functions in conformance with

the SONET/ SDH/ Gigabit Ethernet/ Fibre

Channel/ HDTV/ ESCON/ DTV/ D1 transmission

standards. The device is suitable for SONET-

based WDM applications. The diagram in Figure

1 shows a typical network application.

On-chip clock synthesis is performed by the

high-frequency Phase-Lock Loop (PLL) on the

S3485 transceiver chip, allowing the use of a

slower external transmit clock reference. The

chip can be used with a divide by 16 reference

clock in support of existing system clocking

schemes.

The low-jitter parallel LVDS interface is

compliant with the bit-error rate requirements

of the Telecordia and ITU-T standards. The

S3485 is packaged in a 121 PBGA offering

designers a small package outline.

(NIAGRA)

S19208

AM CC

S3485

AM CC

S3485

AM CC

S3485

AM CC

S3485

System Block Diagram with the S3485

OTX

O RX

Overview

The S3485 transceiver implements SONET/

SDH/ Gigabit Ethernet/ Fibre Channel/ HDTV/

ESCON/ DTV/ D1 serialization/deserialization

and transmission functions. This chip can be

used to implement the front end of SONET/

SDH/ Gigabit Ethernet/ Fibre Channel/ HDTV/

ESCON/ DTV/ D1 equipment, which consists

primarily of the serial transmit interface and the

serial receive interface. The chip handles all the

functions of these two elements, including

parallel-to-serial and serial-to-parallel

conversion, clock generation, and system

timing. The system timing circuitry consists of

data stream management and clock

distribution throughout the front end. Of the

listed bit rates, only the associated SONET/SDH,

Fibre Channel and Gigabit Ethernet protocols

have been validated to their respective

standards. AMCC has characterized the

remaining bit rates with a PRBS 2

has not validated their associated protocols

against any known standard. It is the

responsibility of the end user to evaluate and

verify protocol/standards compliance for all

other bits rates that are intend for use.

O RX

ORX

OTX

PRODUC T BRIEF

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(NIAGRA)

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s3485 Summary of contents

Page 1

... On-chip High-Frequency PLL for Clock Genera- high-frequency Phase-Lock Loop (PLL) on the tion and Clock Recovery • 4-bit LVDS Parallel Data Path S3485 transceiver chip, allowing the use of a • TX and RX Lock Detect Indication slower external transmit clock reference. The • Serial Loop Timing Mode chip can be used with a divide by 16 reference • ...

Page 2

... AMCC is a registered trademark of Applied Micro Circuits Corporation. PowerPC and the PowerPC logo are registered trademarks of IBM Corporation. All other trademarks are the www.amcc.com property of their respective holders. Copyright © 2006 Applied Micro Circuits Corporation. All Rights Reserved. S3485_PB0832_v2.02_20061031 SPECIFIC AT IONS The sequence of operations is as follows: Transmitter Operations • ...

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