sx1231h Semtech Corporation, sx1231h Datasheet - Page 47

• Manufacturer Part Number: sx1231h
• Description: Low Power Integrated Uhf Transceiver With On-chip +20dbm Pa
• Manufacturer: Semtech Corporation

During the comparison of the demodulated data, the first bit received is compared with bit 7 (MSB) of RegSyncValue1 and
the last bit received is compared with bit 0 (LSB) of the last byte whose address is determined by the length of the Sync
word.
When the programmed Sync word is detected the user can assume that this incoming packet is for the node and can be
processed accordingly.
SyncAddressMatch is cleared when leaving Rx or FIFO is emptied.
5.2.3.2. Configuration
Note
5.2.4. Packet Handler
The packet handler is the block used in Packet mode. Its functionality is fully described in section 5.5.
5.2.5. Control
The control block configures and controls the full chip's behavior according to the settings programmed in the configuration
registers.
5.3. Digital IO Pins Mapping
Six general purpose IO pins are available on the SX1231H, and their configuration in Continuous or Packet mode is
controlled through RegDioMapping1 and RegDioMapping2.
Rev 1 - Oct 2011
ADVANCED COMMUNICATIONS & SENSING
Size: Sync word size can be set from 1 to 8 bytes (i.e. 8 to 64 bits) via SyncSize in RegSyncConfig. In Packet mode this
field is also used for Sync word generation in Tx mode.
Error tolerance: The number of errors tolerated in the Sync word recognition can be set from 0 to 7 bits to via SyncTol.
Value: The Sync word value is configured in SyncValue(63:0). In Packet mode this field is also used for Sync word
generation in Tx mode.
SyncAddressMatch
(NRZ)
DCLK
Rx DATA
SyncValue choices containing 0x00 bytes are not allowed
Sync_value[x]
Bit N-x =
Figure 28. Sync Word Recognition
Sync_value[1]
Bit N-1 =
Page 47
Sync_value[0]
Bit N =
SX1231H
DATASHEET
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