xe1205 Semtech Corporation, xe1205 Datasheet
xe1205
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xe1205 Summary of contents
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... The XE1205 is optimized for low power consumption while offering high RF output power and channelized operation suited for both the European (ETSI EN 300- 220-1) and the North American (FCC part 15) regulatory standards ...
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... Pattern register ................................................................................................................................................................... 33 7.2.7 OSCParam configuration register (oscillator parameters) ............................................................................................... 34 7.2.8 ADParam configuration register (additional settings) ....................................................................................................... 35 7.3 Operating Modes ................................................................................................................................................................ 36 7.3.1 XE1205 switching time using SPI_CONFIG interface...................................................................................................... 36 7.3.2 XE1205 switching time using SW(1:0) pins. ..................................................................................................................... 38 7.4 Selection of the reference frequency................................................................................................................................. 38 7.5 Clock output interface......................................................................................................................................................... 39 7.6 Default settings at power-up .............................................................................................................................................. 39 7.7 Pad configuration versus chip modes................................................................................................................................ 40 8 Application information ................................................................................................................................................... 41 8 ...
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... The XE1205 single-chip solution is an integrated circuit intended for use as a low cost FSK transceiver to establish a frequency-agile, half-duplex, bi-directional RF link, with non-return to zero data coding. The device is available in a VQFN 48 package and is designed to provide a fully functional multi-channel FSK transceiver intended for applications in the 433 MHz and 868 MHz European bands and the North American 915 MHz ISM band ...
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... Output of -ChI low-pass filter Test pin (should be grounded in normal operation) Test pin (should be grounded in normal operation) Test pin (should be grounded in normal operation) Test pin (should be grounded in normal operation) Not connected (should be grounded) Not connected (should be grounded) Table 1: Pin description 4 XE1205 www.semtech.com ...
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... Table 3: Operating Range Conditions Quartz oscillator (39 MHz) enabled RFOP = 5 dBm RFOP = 15 dBm Mode A Mode B Mode A Mode B Programmable funw = MHz and 1.995 MHz LO Mode A Mode B Programmable (1) 5 XE1205 Min. Max. Unit -0.5 3.9 V -55 125 °C 0 dBm Min. Max. Unit 2.4 3.6 V -40 85 °C ...
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... Receiver enabled Fundamental or third harmonic Exact step is XTAL / 77 824 (5) Mode A , low range:VTHR1 VTHR2 VTHR3 Mode A, high range:VTHR1 VTHR2 VTHR3 (3) % VDD % VDD % VDD % VDD Table 4: Electrical Specifications 6 XE1205 Min Typ Max Unit dBc dBc dBc (4) 1.2 - 304.7 kbit/s ...
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... MHz, 868 MHz, and 915 MHz with a same 39MHz reference crystal and uses 2-level FSK modulation. Operation of the XE1205 over the frequency range 180 MHz - 1000 MHz beyond the ISM bands described above can be achieved by modifying the reference oscillator crystal frequency. Please contact Semtech for more details. ...
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... RECEIVER SECTION The XE1205 is set to receive mode when MCParam_Select_mode is low by setting MCParam_Chip_mode(1: MCParam_Select_mode is high the XE1205 is set to receive mode by setting SW(1: 5.2.1 LNA & Receiver modes The LNA of the receiver has two programmable operation modes: the high sensitivity mode, Mode A, for reception of weak signals ...
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... BR where Df is the frequency deviation and BR the bit rate. © Semtech 2007 RXParam_Disable_bitsync data BIT SYNCHRONIZER dclk RSSI RSSI_irq Figure 2: Receiver chain in continuous mode 9 XE1205 1 0 IRQ_1(DCLK) RXParam_Pattern IRQParam_Rx_irq_0(1:0) PATTERN MATCHING pattern of the input signal meets the following DATA IRQ_0 www.semtech.com ...
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... IRQ_0) is driven by the output of this comparator and is synchronized by DCLK set to high when a matching condition is detected, otherwise set to low. PATTERN output is updated at the rising edge of DCLK. The © Semtech 2007 Figure 3: Bit synchronizer timing diagram and sent alternatively XE1205 or from to every 8 bits during data www.semtech.com ...
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... RF signal RFFIL Description £ VTHR1 RFFIL £ VTHR2 VTHR1 < RFFIL £ VTHR3 VTHR2 < RFFIL VTHR3 < RFFIL Table 7: RSSI status description 10 kHz, 400 ms for 5 kHz < XE1205 7 kHz, and 500 www.semtech.com ...
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... Semtech 2007 Read RSSI TS_RSSI TS_RSSIM val1 val2 xxx xxx Figure 5: RSSI measurement timing diagram Clear interrupt FEI .This function provides information about the frequency error 12 XE1205 Read RSSI val3 val4 val1 val4 www.semtech.com ...
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... Where int(x) is the integer value of the signed binary representation of x. 5.2.3.6 Frequency Error Correction XE1205 offers two possibilities to correct the RF frequency error either by using FEI block with external microcontroller setting the corrected LO_Frequency or by using the internal Automatic Frequency error Cancellation (AFC). When using FEI block, RXParam without further calculation by a microcontroller since the PLL step is 500 Hz i ...
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... RXParam_Pattern = data BIT dclk SYNCHRONIZER Shift reg FIFO RSSI_irq RSSI 8 Figure 8: Receiver chain in buffered mode 14 . The DATA pin is then set permanently PATTERN MATCHING 8 pattern write_byte /fifoempty Fifofull SPI DATA regspidata XE1205 in case the IRQ_0 IRQ_1 MOSI MISO SCK NSS_DATA www.semtech.com ...
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... Semtech 2007 must be written to IRQParam_Fifooverrun; this clears the contents of the should be written in IRQParam_start_detect (bit 6 add 6). pattern Figure 9: Start detection and FIFO filling 15 XE1205 to IRQParam_Start_detect b10 b11 b12 b13 b12 b11 b10 ...
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... Frequency Error Indicator in buffered mode In buffered mode the Frequency Error Indication operates the same way as in continuous mode. Please refer to section 5.2.3.5 for more details. © Semtech 2007 Byte 14 Byte 15 Figure 10: Completion of FIFO filling FEI 16 XE1205 Completion of FIFO filling Byte 16 Byte 17 www.semtech.com ...
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... TParam_Code_BW(8:0) Sensitivity RFS (BER=0.1%) X -117.5 dBm 139 -118 dBm 160 -119 dBm 185 -119.5 dBm 17 XE1205 Adjacent Channel Rejection RFS ACR (25 kHz offset single tone) 20 dBc 25 dBc 30 dBc 35 dBc Adjacent Channel Rejection ACR (25 kHz offset single tone) 18 dBc 23 dBc ...
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... TRANSMITTER SECTION The XE1205 is set to transmit mode when MCParam_Select_mode is low by setting MCParam_Chip_mode(1: MCParam_Select_mode is high the XE1205 is set to transmit mode by setting pins SW(1: The data directly modulates the LO (optional) pulse shaping filter can be used resulting in an adjacent channel power down to -37dBm at 25kHz for an output power up to 10dBm. ...
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... The filtering option can be used for all bit rates specified in section 5.2.3.2 and for the following frequency deviations. Table 11: Available frequency deviations when using the filtering option © Semtech 2007 Figure 12: Pre-filtering of bit stream in transmit mode Freq_dev(8:0) Frequency deviation (kHz) 000000101 000001010 000010100 000101000 001010000 010100000 101000000 19 XE1205 2 160 www.semtech.com ...
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... Semtech 2007 0 Data shaping 1 filter dclk FIFO Figure 13: Transmit chain in buffered mode to it. At the same time this clears the contents of the FIFO XE1205 IRQ_0 /fifoempty shift register IRQ_1 MOSI SPI MISO SCK NSS_DATA and the previous FIFO contents will be www.semtech.com ...
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... CLKOUT is defined by the value of the OSCParam_Clkout_freq(2:0) parameter. The output frequency at CLKOUT is the reference oscillator frequency divided 32. With a reference oscillator frequency of 39 MHz this provides a reference clock at 19.5 MHz, 9.75 MHz, 4.87 MHz, 2.44 MHz or 1.22 MHz, respectively. This clock signal is disabled in Sleep Mode. © Semtech 2007 21 XE1205 www.semtech.com ...
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... HIGHEST BIT RATES: EXAMPLE OF 304.7 KBIT/S OPERATION XE1205 is able to sustain other bit rates between 152.34 kbit/s and 304.7 kbit/s using OSR_minus_1 register as described in section 5.2.3. recommended whenever possible to use a modulation index ( =2 f/BR) 2 whenever possible. For the highest bit rates the receiver filter bandwidth will limit the maximal usuable . Lower modulation indexes should be used then ...
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... Sensitivity@0.1%: -102 dBm in mode A and -90 dBm in mode B. · ACR@1MHz offset, single tone: 25 dBc. © Semtech 2007 434 MHz 869 MHz 915 MHz 3 220 pF 150 pF 1.5 kW 1.5 kW Table 15: PLL Loop Filter Bill of Material for 304.7 kbit/s 23 XE1205 Tolerance 10 nF ± 5% ± 5% 150 pF ± 5% 1.5 kW www.semtech.com ...
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... SERIAL CONTROL INTERFACE The XE1205 contains two SPI-compatible serial interfaces, one to send and read the chip configuration, the other to send and receive data in buffered mode. Both interfaces are configured in slave mode and share the same pins MISO (Master In Slave Out), MOSI (Master Out Slave In), SCK (Serial Clock). Two additional pins are required to select the SPI interface: NSS_CONFIG to change or read the transceiver configuration, and NSS_DATA to send or read data ...
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... A1, the previous contents of A1 can be read by the micro-controller Figure 15: Write sequence when sending a new configuration to the XE1205 via the SPI _CONFIG NSS_CONFIG must remain low during the transmission of the two bytes (address and data goes high after the first byte, then the next byte will be considered as an address byte ...
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... NSS_DATA signal back to high and back to low between each transmitted or received byte. © Semtech 2007 A(3) A(2) A(1) A(0) stop D(7) D(6) D(5) D(4) D(3) D(2) D(1) 26 XE1205 The SPI_DATA interface is then selected D(0) HZ www.semtech.com ...
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... D1(3) D1(2) D1(1) D1(0) x Byte 1 to read Figure 17 Writing 2 bytes in transmitter mode Byte 1 to read D1(4) D1(3) D1(2) D1(1) D1(0) HZ Figure 18: Reading 2 bytes in receive mode. 27 XE1205 D2(7) D2(6) D2(5) D2(4) D2(3) D2(2) D2(1) Byte 2 to read ...
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... CONFIGURATION AND STATUS REGISTERS The XE1205 has several operating modes, configuration parameters and internal status registers that may be accessed by the microcontroller via the SPI_CONFIG interface. The switching pins SW(1:0) allows switching between one of the four operating modes (sleep, stand-by, receive, transmit) when MCParam_Select_mode is high. If MCParam_Select_mode is low, the modes are defined by the register through the SPI_CONFIG interface and SW(1:0) may be used as an output to control, for example, an antenna switch ...
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... MCParam_Br(6:0) 1 -> Konnex mode-> bit rate = 32.7 kbit/s r/w Bit rate Br = 152.34e3/(int(Br Where int(x) = integer value of the binary representation of x. Example: 0000001 -> 76.1 kbit/s 1111111 -> 1.19 kbit/s Note: if Konnex mode is enabled, then bit rate = 32.7 kbit/s. 29 XE1205 www.semtech.com ...
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... The FIFO is filled as long as Start_detect is high r/w/c Start of FIFO filling If start_fill = goes high when a start sequence is detected writing a clears the bit and wait for a new start sequence If start_fill = , 1 -> start to fill the FIFO, 0 -> stop to fill the FIFO. 30 XE1205 (6) clear FIFO after Overrun occurred www.semtech.com ...
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... RESERVED Table 19: TXParam configuration register RW Description r/w Bit synchronizer on/off: 0 -> -> OFF r/w Bandwidth of the base band filter(SSB): must be 00 -> 10 kHz 01 -> 20 kHz 10 -> 40 kHz 11 -> 200 kHz r/w Forces the bandwidth of the base band filter to its maximum value 31 XE1205 ) Freq_dev + Br/2 www.semtech.com ...
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... IQ amplifier off/on: 0 -> off 1 -> on r/w Linearity/sensitivity mode 0 -> Mode A (high sensitivity) 1 -> Mode B (high linearity) r/w Pattern recognition off/on: 0 -> off 1 -> on r/w Size of the reference Pattern: 00 -> 8 bits 01 -> 16 bits 10 -> 24 bits 11 -> 32 bits 32 XE1205 VTHR2 VTHR3 www.semtech.com ...
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... Bit 0 Bit 7 Bit 0 10010011 10010011 Table 22: Pattern recognition example (32 bits) Byte Address 15 Bit 0 Bit 7 Bit 0 Xxxxxxxx Table 23: Pattern recognition example (8 bits) 33 XE1205 nd byte is stored at address 14, the Byte Address 16 Bit 7 Bit 0 10101010 10101010 last bit received Byte Address 16 Bit 7 Bit 0 Xxxxxxxx www.semtech.com ...
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... Tx filter 0 -> disabled 1 -> enabled r/w RESERVED Table 24: OSCParam configuration register 34 XE1205 www.semtech.com ...
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... Flag allowing the over-sampling ratio of the bit synchronizer to be r/w changed: 0 -> default OSR (32) 1 -> OSR defined by TParam_OSR(7:0) Over-sampling ratio of the bit synchronizer when r/w TParam_Chg_OSR = 1 Actual OSR = TParam_OSR(7: Table 25: Useful special settings from TParam register 35 XE1205 www.semtech.com ...
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... OPERATING MODES The XE1205 has four main operating modes illustrated in Table 26 below. These modes are defined by register MCParam_Chip_mode(1:0) when bit MCParam_Select_mode is low and defined by SW(1:0) pins when MCParam_Select_mode is high. Please note that in both cases the changes will be applied to the transceiver upon the rising edge of the NSS_CONFIG signal (ie NSS_CONFIG must be set low even when using SW(1:0) as inputs) ...
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... Programmed mode NSS_CONFIG Actual mode © Semtech 2007 Sleep Stand-by Sleep Stand-by TS_OS Transmit Transmit Figure 21 Sequence from transmit to receive mode. Receive Receive Figure 22: Sequence from receiver to transmitter mode 37 XE1205 Transmit Transmit TS_STR Receive Receive TS_RE Transmit Transmit TS_TR www.semtech.com ...
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... NSS_CONFIG Actual frequency Figure 24. Switching between two carrier frequencies in transmit mode. 7.3.2 XE1205 switching time using SW(1:0) pins. If MCParam_Select_mode is high then the transceiver mode is fixed by SW(1:0) pins and register MCParam_Chip_mode can be used in read mode but has no effect on the transceiver mode. 7.4 SELECTION OF THE REFERENCE FREQUENCY The reference clock used for the frequency synthesizer and the internal digital circuitry may be generated by either an external 39 MHz quartz crystal or a TCXO or an external clock ...
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... In the case of overtone operation where the microcontroller uses the XE1205 as a clock source, the user should note that during the power up sequence of the XE1205, the oscillator may start and run at its fundamental frequency until the correct value of parallel resistor in the register OSCParam_Resxosc(3:0) is programmed. Before time-sensitive operations an oscillator settling period should be observed to ensure the desired oscillation frequency ...
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... NSS_CONFIG= NSS_CONFIG= or NSS_DATA = or NSS_DATA = else else High Impedance High Impedance INPUT INPUT INPUT INPUT Table 28. Pad configuration vs chip modes 40 XE1205 Transmit Comment OUTPUT when If Select_mode = Select_mode = SW0 and SW1 else defines the chip Input mode OUTPUT when If Select_ mode = Select mode = ...
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... APPLICATION INFORMATION This section provides details of the recommended component values for the frequency dependant blocks of the XE1205. Note that these values are dependent upon circuit layout and PCB structure, and that decoupling components have been omitted for clarity. 8.1 MATCHING NETWORK OF THE RECEIVER The schematic of the matching network at the input of the receiver is given below (for a source impedance of 50W) ...
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... The Smith charts in Figure 26 and Figure 27 below show contours of output power versus load impedance when the highest output level is selected (15 dBm mode). 0.3 0.2 0.1 0.1 0.2 0.1 0.2 0.3 © Semtech 2007 869 MHz 15 dBm 0.8 0.9 1 0.6 0.5 0.4 0.5 1 0.4 0.5 0.6 0.8 0.9 1 Figure 26: Output power vs. load impedance at 869 MHz. 42 XE1205 1.4 1.2 1.6 1 dBm 14 dBm 12 dBm 2.4 2 1.8 1.6 1.2 1 ...
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... Semtech 2007 915 MHz 15 dBm 1 0 Figure 27: Output power vs. load impedance at 915 MHz. 43 XE1205 www.semtech.com ...
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... Table 31: Matching circuit component values 434 MHz 869 MHz 1 6.8 nH Table 32: VCO tank component values 44 XE1205 VDD CT2 XE1205 RFOUT LT2 Typical Value Tolerance for 915 MHz 1.8 pF ± ± ± 5% 3.3 pF ± 5% 2.2 pF ± ± ...
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... Semtech 2007 RL1 CL2 CL1 VSS Figure 29: Frequency synthesizer loop filter 434 MHz 869 MHz 560W 560W Table 33: Typical frequency synthesizer component values 45 XE1205 LFB XE1205 915 MHz Tolerance 10 nF ± ± 5% ± 5% 680W www.semtech.com ...
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... The overtone crystal usage can result in higher oscillator start-up time than fundamental mode. The overtone crystal should be designed for Cload = and has parameters of Rm < 60W, C0 < 7 pF. © Semtech 2007 Min. value - - - - - - - - Table 34: Crystal characteristics 46 XE1205 Typ. value Max. value 39.0 MHz - (fundamental 40W - ...
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... PACKAGING INFORMATION XE1205 comes in a 48-lead VQFN 8X8 package as shown in Figure 30 below. © Semtech 2007 Figure 30: Package dimensions 47 XE1205 www.semtech.com ...
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... Semtech and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs damages and attorney fees which could arise. Contact Information © Semtech 2007 Semtech Corporation Wireless and Sensing Products Division 200 Flynn Road, Camarillo, CA 93012 Phone (805) 498-2111 Fax : (805) 498-3804 48 XE1205 www.semtech.com ...