stac9708 ETC-unknow, stac9708 Datasheet - Page 20

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stac9708

Manufacturer Part Number
stac9708
Description
Multi-channel Ac97 Codec With Multi-codec Option
Manufacturer
ETC-unknow
Datasheet

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stac9708T
Manufacturer:
SIGMATEL
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SigmaTel, Inc.
A new audio input frame begins with a low to high transition of SYNC. SYNC is synchronous to the
rising edge of BIT_CLK. On the immediately following falling edge of BIT_CLK, STAC9708/11
samples the assertion of SYNC. This falling edge marks the time when both sides of AC-Link are
aware of the start of a new audio frame. On the next rising of BIT_CLK, the STAC9708/11 transitions
SDATA_IN into the first bit position of slot 0 ("Codec Ready" bit). Each new bit position is presented
to AC-Link on a rising edge of BIT_CLK and subsequently sampled by the AC'97 controller on the
following falling edge of BIT_CLK. This sequence ensures that data transitions, and subsequent
sample points for both incoming and outgoing data streams are time aligned.
SDATA_IN's composite stream is MSB justified (MSB first) with all non-valid bit positions (for
assigned and/or unassigned time slots) stuffed with 0's by STAC9708/11. SDATA_IN data is sampled
on the falling edges of BIT_CLK.
3.1.2.1 Slot 1: Status Address Port
The status port is used to monitor status for STAC9708/11 functions including, but not
limited to, mixer settings, and power management.
Audio input frame slot 1’s stream echoes the control register index, for historical reference,
for the data to be returned in slot 2. (Assuming that slots 1 and 2 had been tagged “valid” by
STAC9708/11 during slot 0)
Status Address Port hit assignments:
Bit (19)
Bit (18;12) Control Register Index
Bit (11:0)
The first bit (MSB) generated by STAC9708/11 is always stuffed with a 0. The following 7
bit positions communicate the associated control register address, and the trailing 12 bit
positions are stuffed with 0's by STAC9708/11.
SDATA_IN
BIT_CLK
SYNC
RESERVED
RESERVED
End of previous audio frame
Figure 9. Start of an Audio Input Frame
STAC9708 samples SYNC assertion here
Preliminary
Ready
Codec
20
STAC9708 samples first SDATA_OUT bit of frame here
slot1
(Stuffed with 0)
(Stuffed with 0's)
(Echo of register index for which data is being returned)
slot2
STAC9708/11
10/02/98

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