hi-3599pst Holt Integrated Circuits, Inc., hi-3599pst Datasheet - Page 7

• Manufacturer Part Number: hi-3599pst
• Description: Octal Arinc 429 Receivers With Label Recognition And Spi Interface
• Manufacturer: Holt Integrated Circuits, Inc.

FUNCTIONAL DESCRIPTION (cont.)
Once a valid ARINC word is loaded into the FIFO, the EOS signal
clocks the Data Ready flip-flop to a "1", and the corresponding
channel’s Status Register FIFO Empty bit (SR0- SR7) goes to a
“0”. The channel’s Empty bit remains low until the corresponding
Receive FIFO is empty. Each received ARINC word is retrieved
via the SPI interface using SPI instruction n3 hex where “n” is the
channel number 1-8 hex.
Up to 4 ARINC words may be held in each channel’s Receive
FIFO. The Status Register FIFO Full bit (SR8 - SR15) goes high
when the corresponding channel’s Receive FIFO is full. Failure to
offload a full Receive FIFO causes additional received valid
ARINC words to overwrite the last received word.
LABEL RECOGNITION
The user loads the 16 byte label look-up table to specify which 8-
bit incoming ARINC labels are captured by the receiver, and
which are discarded. If fewer than 16 labels are required, spare
label memory locations must be filled with duplicate copies of any
valid label. After the look-up table is initialized, set channel
Control Register bit CR2 to enable label recognition for that
channel.
If label recognition is enabled, the receiver compares the label in
each new ARINC word against the channel’s stored label look-up
table. If a label match is found, the received word is processed. If
no match occurs, the new ARINC word is discarded and no
indicators of received ARINC data are presented. Note that 00
hex is treated in the same way as any other label value. Label
memory bit significance is not changed by the status of Control
Register bit CR9. The most significant label bit is always
compared to the first (MSB) bit of each SPI 8-bit data field from
SPI instruction n1 hex, where “n” is the channel number 1-8 hex.
If a channel Control Register CR2 bit equals ”0,” the
corresponding receiver recognizes all label values as valid, as
shown in Table 3.
READING THE LABEL MEMORY
The contents of each channel’s Label Memory may be read via
the SPI interface using instruction n2 hex where “n” equals the
channel number 1-8 hex, as described in Table 1.
SELF TEST
The HI-3598 and HI-3599 contain an on-chip ARINC 429 format
self-test register which may be used to execute user-defined self-
test sequences for each receiver. A 32-bit test word is loaded to
the Test Register using SPI instructions n8 hex (for ARINC 429
high-speed data rate) or n9 hex (for ARINC 429 low speed). Upon
completion of the instruction, the word is shifted out of the register
and routed to all receivers. The serial test word may be observed
at the HI-3598’s TX1 and TX0 pins, as shown in Table 4. Each
channel will respond to the test word if self-test mode is enabled
for that channel (Control Register CR5 bit equals “0”) and the
receive channel is set to the correct speed. If a channel’s CR5 bit
equals “1” the channel ignores the self-test word and continues to
respond to the external ARINC 429 bus.
The first bit shifted into the Self Test register will be the first bit sent
to the receivers and the TX1 and TX0 pins. In ARINC 429
protocol, this bit is the LSB. Therefore the Self Test word is unique
in that it is loaded LSB first with respect to the ARINC word.
HOLT INTEGRATED CIRCUITS
HI-3598, HI-3599
7
TRANSMIT FUNCTION
The self test register can be used as a transmitter by connecting
the TX1 and TX0 pins to an external ARINC 429 line driver (such
as the HI-8570 or HI-8571).
LINE RECEIVER INPUT PINS
The HI-3598 has two sets of Line Receiver input pins, RINA/B
and RINA/B-40. Only one pair may be used to connect to the
ARINC 429 bus. THE RINA/B pins may be connected directly to
the ARINC 429 bus. The RINA/B-40 pins require an external
40KOhm resistor to be added in series with each ARINC input
without affecting the ARINC input thresholds. This option is espe-
cially useful in applications where lightning protection circuitry is
also required.
When using the RINA/B-40 pins, each side of the ARINC bus
must be connected through a 40K ohm series resistor in order
for the chip to detect the correct ARINC levels. The typical 10
volt differential signal is translated and input to a window com-
parator and latch. The comparator levels are set so that with the
external 40K ohm resistors, they are just below the standard 6.5
volt minimum ARINC data threshold and just above the standard
2.5 volt maximum ARINC null threshold.
When using the reduced pin-count HI-3599 option of this prod-
uct, only one set of ARINC 429 receive inputs are provided for
each channel. The standard HI-3599 device uses the direct-
connection RINA / RINB pins. The HI-3599-40 device uses the
RINA-40 / RINB-40 pins and requires external 40K ohm series
resistors. See the ordering information table for complete part
number options.
Please refer to the Holt AN-300 Application Note for additional
information and recommendations on lightning protection of Holt
line drivers and line receivers.
MASTER RESET (MR)
Assertion of Master Reset (MR) causes immediate termination
of data reception. The eight Receive FIFOs are cleared. Status
Register FIFO flags and FIFO status output signals are also
cleared. Master Reset does not affect the eight channel Control
Registers. Master Reset may be asserted using the MR input
pin (HI-3598 only) or by executing SPI instruction n7 hex.
An individual receive channel can be reset by setting its
corresponding Control Register CR3 bit to “1”. This clears the
channel’s receiver logic and Receive FIFO and disables the
receiver until CR3 is reset to “0”. For applications requiring less
than eight channels, unused receivers should be held in reset
by setting the corresponding Control Register CR3 bits.
TX1
0
1
0
Table 4. Test Outputs
TX0
0
0
1
ARINC 429 State
ZERO
NULL
ONE