am41dl16x4d Meet Spansion Inc., am41dl16x4d Datasheet - Page 59
![no-image](/images/no-image-200.jpg)
am41dl16x4d
Manufacturer Part Number
am41dl16x4d
Description
Stacked Multi-chip Package Mcp Flash Memory And Sram Am29dl16xd 16 Megabit 2 M X 8-bit/1 M X 16-bit Cmos 3.0 Volt-only, Simultaneous Operation Flash Memory And 4 Mbit 512 K X 8-bit/256 K X 16-bit Static Ram
Manufacturer
Meet Spansion Inc.
Datasheet
1.AM41DL16X4D.pdf
(63 pages)
- Current page: 59 of 63
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AC CHARACTERISTICS
Notes:
1. UB#s and LB#s controlled, CIOs must be high.
2. t
3. t
4. t
5. A write occurs during the overlap (t
58
asserting UB#s or LB#s for a single byte operation or simultaneously asserting UB#s and LB#s for a double byte operation. A
write ends at the earliest transition when CE1#s goes high and WE# goes high. The t
to the end of write.
CW
WR
AS
is measured from the address valid to the beginning of write.
is measured from CE1#s going low to the end of write.
is measured from the end of write to the address change. t
CE1#s
CE2s
Address
UB#s, LB#s
WE#
Data In
Data Out
Figure 32. SRAM Write Cycle—UB#s and LB#s Control
WP
) of low CE#1 and low WE#. A write begins when CE1#s goes low and WE# goes low when
High-Z
(See Note 4)
P R E L I M I N A R Y
t
AS
Am41DL16x4D
WR
(See Note 2)
t
applied in case a write ends as CE1#s or WE# going high.
CW
t
t
AW
WC
(See Note 5)
t
t
CW
(See Note 2)
BW
t
WP
t
DW
Data Valid
WP
is measured from the beginning of write
t
WR
t
DH
(See Note 3)
High-Z
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