am41pds3224d Meet Spansion Inc., am41pds3224d Datasheet - Page 11

• Manufacturer Part Number: am41pds3224d
• Description: 32 Mbit 2 M ? 16-bit Cmos 1.8 Volt-only, Simultaneous Operation Page Mode Flash Memory And 4 Mbit 512 K ? 8-bit/256 K ? 16-bit Static Ram Preliminary
• Manufacturer: Meet Spansion Inc.

MCP DEVICE BUS OPERATIONS
This section describes the requirements and use of
the device bus operations, which are initiated through
the internal command register. The command register
itself does not occupy any addressable memory loca-
t io n. Th e re g ist e r is a la t ch u se d t o st or e t h e
commands, along with the address and data informa-
tion needed to execute the command. The contents of
Legend: L = Logic Low = V
SADD = Flash Sector Address, A
Notes:
1. Other operations except for those indicated in this column are inhibited.
2. Do not apply CE#f = V
3. Don’t care or open LB#s or UB#s.
4. If WP#/ACC = V
5. The sector protect and sector unprotect functions may also be implemented via programming equipment. See the “Sector/Sector Block Protection
6. If WP#/ACC = V
10
Operation
(Notes 1, 2)
Read from Flash
Write to Flash
Standby
Output Disable
Flash Hardware
Reset
Sector Protect
(Note 5)
Sector Unprotect
(Note 5)
Temporary Sector
Unprotect
Read from SRAM
Write to SRAM
If WP#/ACC = V
and Unprotection” section.
on whether they were last protected or unprotected using the method described in “Sector/Sector Block Protection and Unprotection”. If
WP#/ACC = V
HH,
IL
ACC
IL
, the boot sectors will be protected. If WP#/ACC = V
, the two outermost boot sectors remain protected. If WP#/ACC = V
all sectors will be unprotected.
V
CE#f
0.3 V
(9V), the program time will be reduced by 40%.
CC
H
H
L
L
L
X
L
L
X
IL
, CE1#s = V
Table 1. Device Bus Operations—SRAM Word Mode, CIOs = V
IL
, H = Logic High = V
CE1#s
IN
H
H
H
H
H
H
H
X
X
X
L
X
X
X
X
L
L
= Address In, D
IL
CE2s OE# WE#
and CE2s = V
X
X
X
H
X
X
X
X
H
H
L
L
L
L
L
L
L
IH
H
X
H
H
X
H
H
X
X
L
L
, V
IN
ID
= Data In, D
P R E L I M I N A R Y
IH
= 9–11 V, V
at the same time.
H
X
H
H
X
X
H
L
L
L
L
Am41PDS3224D
SA
X
X
X
X
X
X
X
X
X
X
X
OUT
HH
= Data Out
A1 = H,
A6 = H,
A1 = H,
= 9.0 ± 0.5 V, X = Don’t Care, SA = SRAM Address Input, Byte Mode,
SADD,
A6 = L,
SADD,
A0 = L
A0 = L
IH
Addr.
A
A
A
A
the boot sectors protection will be removed.
X
X
X
X
X
IN
IN
IN
IN
the register serve as inputs to the internal state ma-
chine. The state machine outputs dictate the function
of the device. Tables 1–2 list the device bus opera-
tions, the inputs and control levels they require, and
the resulting output. The following subsections de-
scribe each of these operations in further detail.
(Note 3)
LB#s
X
X
X
X
X
X
X
X
H
H
L
L
L
L
L
IH
(Note 3)
, the two outermost boot sector protection depends
UB#s
X
X
X
X
X
X
X
X
H
H
L
L
L
L
L
RESET#
V
0.3 V
V
V
V
CC
H
H
H
H
H
L
ID
ID
ID
WP#/ACC
(Note 4)
(Note 4)
(Note 6)
(Note 6)
CC
L/H
L/H
L/H
L/H
L/H
H
X
High-Z
High-Z
High-Z
High-Z
High-Z
DQ7–
May 13, 2002
D
D
D
DQ0
D
D
D
D
D
D
OUT
OUT
OUT
IN
IN
IN
IN
IN
IN
DQ15–
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
D
D
D
DQ8
D
D
D
OUT
X
X
OUT
OUT
IN
IN
IN