am42dl1612d Meet Spansion Inc., am42dl1612d Datasheet - Page 16

• Manufacturer Part Number: am42dl1612d
• Description: 16 Mbit 2 M ? 8-bit/1 M ? 16-bit Cmos And 2 Mbit 128 K ? 16-bit Static Ram Preliminary
• Manufacturer: Meet Spansion Inc.

Standby Mode
When the system is not reading or writing to the de-
vice, it can place the device in the standby mode. In
this mode, current consumption is greatly reduced,
and the outputs are placed in the high impedance
state, independent of the OE# input.
The device enters the CMOS standby mode when the
CE#f and RESET# pins are both held at V
(Note that this is a more restricted voltage range than
V
within V
mode, but the standby current will be greater. The de-
vice requires standard access time (t
access when the device is in either of these standby
modes, before it is ready to read data.
If the device is deselected during erasure or program-
ming, the device draws active current until the
operation is completed.
I
standby current specification.
Automatic Sleep Mode
The automatic sleep mode minimizes Flash device en-
ergy consumption. The device automatically enables
this mode when addresses remain stable for t
30 ns. The automatic sleep mode is independent of
the CE#f, WE#, and OE# control signals. Standard ad-
dr e ss ac c es s ti mi ng s p r ov id e new da ta w he n
addresses are changed. While in sleep mode, output
data is latched and always available to the system.
I
automatic sleep mode current specification.
RESET#: Hardware Reset Pin
The RESET# pin provides a hardware method of re-
setting the device to reading array data. When the
14
CC3
CC4
Am29DL161D
Am29DL162D
Am29DL163D
Am29DL164D
IH
Part Number
.) If CE#f and RESET# are held at V
in the DC Characteristics table represents the
in the DC Characteristics table represents the
Device
CC
± 0.3 V, the device will be in the standby
Megabits
0.5 Mbit
2 Mbit
4 Mbit
8 Mbit
fifteen 64 Kbyte/32 Kword
seven 64 Kbyte/32 Kword
three 64 Kbyte/32 Kword
Table 3. Device Bank Division
Bank 1
Eight 8 Kbyte/4 Kword,
Eight 8 Kbyte/4 Kword,
Eight 8 Kbyte/4 Kword,
Eight 8 Kbyte/4 Kword
CE
CC
IH
) for read
Sector Sizes
, but not
± 0.3 V.
ACC
Am42DL16x2D
+
RESET# pin is driven low for at least a period of t
the device immediately terminates any operation in
progress, tristates all output pins, and ignores all
read/write commands for the duration of the RESET#
pulse. The device also resets the internal state ma-
chine to reading array data. The operation that was
interrupted should be reinitiated once the device is
ready to accept another command sequence, to en-
sure data integrity.
Current is reduced for the duration of the RESET#
pulse. When RESET# is held at V
draws CMOS standby current (I
at V
will be greater.
The RESET# pin may be tied to the system reset cir-
cuitry. A system reset would thus also reset the Flash
memory, enabling the system to read the boot-up firm-
ware from the Flash memory.
If RESET# is asserted during a program or erase op-
eration, the RY/BY# pin remains a “0” (busy) until the
internal reset operation is complete, which requires a
time of t
tem can thus monitor RY/BY# to determine whether
the reset operation is complete. If RESET# is asserted
when a program or erase operation is not executing
(RY/BY# pin is “1”), the reset operation is completed
within a time of t
rithms). The system can read data t
RESET# pin returns to V
Refer to the AC Characteristics tables for RESET# pa-
rameters and to Figure 15 for the timing diagram.
Output Disable Mode
When the OE# input is at V
disabled. The output pins are placed in the high
impedance state.
IL
but not within V
READY
Megabits
15.5 Mbit
14 Mbit
12 Mbit
(during Embedded Algorithms). The sys-
8 Mbit
READY
SS
(not during Embedded Algo-
IH
± 0.3 V, the standby current
.
IH
Bank 2
, output from the device is
64 Kbyte/32 Kword
64 Kbyte/32 Kword
64 Kbyte/32 Kword
64 Kbyte/32 Kword
CC4
Sector Sizes
SS
Twenty-eight
Twenty-four
). If RESET# is held
Thirty-one
± 0.3 V, the device
Sixteen
February 6, 2004
R H
after the
RP
,