am42bds6408g Meet Spansion Inc., am42bds6408g Datasheet - Page 84

• Manufacturer Part Number: am42bds6408g
• Description: 64 Mbit 4 M ? 16-bit Cmos 1.8 Volt-only, Simultaneous Operation, Burst Mode Flash Memory And 8 Mbit 512 K ? 16-bit Static Ram Preliminary
• Manufacturer: Meet Spansion Inc.

SRAM AC CHARACTERISTICS
Write Cycle
Notes:
1. WE# controlled.
2. t
3. t
4. t
5. A write occurs during the overlap (t
82
asserting UB#s or LB#s for a single byte operation or simultaneously asserting UB#s and LB#s for a double byte operation. A
write ends at the earliest transition when CE1#s goes high and WE# goes high. The t
to the end of write.
CW
WR
AS
Parameter
Symbol
is measured from the address valid to the beginning of write.
is measured from CE1#s going low to the end of write.
is measured from the end of write to the address change. t
t
t
t
t
t
t
t
WHZ
t
t
t
t
WC
AW
BW
WP
WR
DW
OW
Address
CE1#s
CE2s
WE#
Data In
Data Out
Cw
DH
AS
Description
Write Cycle Time
Chip Enable to End of Write
Address Setup Time
Address Valid to End of Write
UB#s, LB#s to End of Write
Write Pulse Time
Write Recovery Time
Write to Output High-Z
Data to Write Time Overlap
Data Hold from Write Time
End Write to Output Low-Z
A D V A N C E
WP
Figure 49. SRAM Write Cycle—WE# Control
) of low CE#1 and low WE#. A write begins when CE1#s goes low and WE# goes low when
Data Undefined
High-Z
(See Note 3)
t
AS
Am42BDS6408H
I N F O R M A T I O N
t
WR
WHZ
(See Note 1)
(See Note 1)
t
applied in case a write ends as CE1#s or WE# going high.
AW
t
(See Note 4)
WC
t
t
CW
CW
t
WP
t
DW
Data Valid
Max
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
min
WP
is measured from the beginning of write
t
DH
E6, E7,
t
t
D6, D7
WR
OW
55
45
45
45
45
20
30
0
0
0
0
5
High-Z
E8, E9,
D8, D9
October 23, 2003
70
60
60
60
50
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns