am49dl320bg Meet Spansion Inc., am49dl320bg Datasheet
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... Am49DL320BG Data Sheet July 2003 The following document specifies Spansion memory products that are now offered by both Advanced Micro Devices and Fujitsu. Although the document is marked with the name of the company that orig- inally developed the specification, these products will be offered to customers of both AMD and Fujitsu ...
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... PRELIMINARY Am49DL320BG Stacked Multi-Chip Package (MCP) Flash Memory and SRAM Am29DL320G 32 Megabit ( 8-Bit 16-Bit) CMOS 3.0 Volt-only, Simultaneous Operation Flash Memory and 32 Mbit (2M x 16-Bit) Pseudo Static RAM with Page Mode DISTINCTIVE CHARACTERISTICS MCP Features Power supply voltage of 2.7 to 3.3 volt High performance — ...
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... Bank Twenty-four 64 Kbyte/32 Kword Bank Eight 64 Kbyte/32 Kword Am49DL320BG Features The SecSi TM (Secured Silicon) Sector is an 256 byte extra sector capable of being permanently locked by AMD or cus- tomers. The SecSi Indicator Bit (DQ7) is permanently set the part is factory locked, and set cus- tomer lockable ...
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... Alternate CE#f Controlled Erase and Program Operations .... 52 Figure 27. Flash Alternate CE#f Controlled Write (Erase/Program) Operation Timings.......................................................................... 53 Read Cycle ............................................................................. 54 Figure 28. Psuedo SRAM Read Cycle........................................... 54 Figure 29. Page Read Timing ........................................................ 55 Write Cycle ............................................................................. 56 Figure 30. Pseudo SRAM Write Cycle—WE# Control ................... 56 Figure 31. Pseudo SRAM Write Cycle—CE1#s Control ................ 57 Am49DL320BG vs. Frequency ............................................ 39 CC1 3 ...
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... Power on and Deep Power Down . . . . . 60 Figure 33. Deep Power-down Timing.............................................. Figure 34. Power-on Timing........................................................... 60 pSRAM Address Skew . . . . . . . . . . . . . . . . . . . . . 61 Figure 35. Read Address Skew ..................................................... 61 Figure 36. Write Address Skew...................................................... 61 Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . 62 FLB073—73-Ball Fine-Pitch Grid Array 8 x 11.6 mm ............. 62 Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . 63 Am49DL320BG June 25, 2002 ...
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... Am49DL320BG Flash Memory N/A N RY/BY# 32 MBit Flash Memory DQ15/A–1 to DQ0 V s CCQ SS SSQ 32 MBit DQ15 to DQ0 Pseudo SRAM Am49DL320BG Pseudo SRAM DQ15/A–1 to DQ0 5 ...
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... RESET# CONTROL WE# CE# COMMAND REGISTER BYTE# WP#/ACC DQ15–DQ0 A20– Mux Upper Bank Address Upper Bank RY/BY# X-Decoder Status & Control X-Decoder Lower Bank Lower Bank Address Mux Am49DL320BG OE# BYTE# DQ15–DQ0 Mux June 25, 2002 ...
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... DQ12 DQ7 DQ11 NC DQ5 DQ14 package and/or data integrity may be compromised if the package body is exposed to temperatures above 150 C for prolonged periods of time. Am49DL320BG Flash only A10 NC Pseudo B10 SRAM only NC Shared D9 A15 F10 G10 ...
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... pSRAM Power Supply Device Ground (Common Pin Not Connected Internally LOGIC SYMBOL 21 A20–A0 A-1 SA CE#f CE1#s CE2s OE# WE# WP#/ACC RESET# UB#s LB#s CIOf Am49DL320BG DQ15–DQ0 RY/BY# June 25, 2002 ...
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... Industrial (– +85 C) SPEED OPTION See “Product Selector Guide” on page 5. BOOT CODE SECTOR ARCHITECTURE T = Top sector B = Bottom sector PROCESS TECHNOLOGY G = 0.17 µm PSEUDO SRAM DEVICE DENSITY B = 32Mbits Order Number Am49DL320BGT851 Am49DL320BGB851 Am49DL320BGT701 Am49DL320BGB701 Am49DL320BG Valid Combinations Package Markings T,S M49000000H T,S M49000001A T,S M49000000G T,S M49000001B 9 ...
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... If WP#/ACC = V protected. If WP#/ACC = V protection depends on whether they were last protected or unprotected using the method described in “Autoselect Mode”. If WP#/ACC = V 7. Data will be retained in pSRAM. 8. Data will be lost in pSRAM. Am49DL320BG IH WP#/ACC DQ7– DQ15– (Note 4) DQ0 DQ8 ...
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... If WP#/ACC = V protected. If WP#/ACC = V protection depends on whether they were last protected or unprotected using the method described in “Autoselect Mode”. If WP#/ACC = V 7. Data will be retained in pSRAM. 8. Data will be lost in pSRAM. Am49DL320BG IL WP#/ACC DQ7– DQ15– (Note 4) DQ0 DQ8 ...
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... An erase operation may also be sus- pended to read from or program to another location within the same bank (except the sector being erased). Figure 21 shows how read and write cycles Am49DL320BG on this pin, the device auto- HH must not be asserted on HH ...
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... Refer to the pSRAM AC Characteristics tables for RE- SET# parameters and to Figure 15 for the timing dia- gram. Output Disable Mode When the OE# input disabled. The output pins are placed in the high impedance state. Am49DL320BG RP ±0.3 V, the device SS f). If RESET# is CC4 ±0.3 V, the standby cur- SS (during Embedded Algorithms) ...
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... Am49DL320BG (x16) Address Range 000000h–07FFFh 008000h–0FFFFh 010000h–17FFFh 018000h–01FFFFh 020000h–027FFFh 028000h–02FFFFh 030000h–037FFFh 038000h–03FFFFh 040000h–047FFFh 048000h–04FFFFh 050000h–057FFFh 058000h–05FFFFh 060000h– ...
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... Top Boot SecSi Sector Addresses Sector Address Sector Size A20–A12 (Bytes/Words) 111111xxx 256/128 Am49DL320BG (x16) Address Range 180000h–187FFFh 188000h–18FFFFh 190000h–197FFFh 198000h–19FFFFh 1A0000h–1A7FFFh 1A8000h–1AFFFFh 1B0000h–1B7FFFh 1B8000h–1BFFFFh 1C0000h–1C7FFFh 1C8000h–1CFFFFh 1D0000h– ...
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... Am49DL320BG (x8) (x16) Address Range 000000h–000FFFh 001000h–001FFFh 002000h–002FFFh 003000h–003FFFh 004000h–004FFFh 005000h–005FFFh 006000h–006FFFh 007000h–007FFFh 008000h–00FFFFh 010000h–017FFFh 018000h–01FFFFh 020000h– ...
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... A20:A0 in word mode (BYTE#=V IL Bottom Boot SecSi Sector Addresses Sector Address Sector Size A20–A12 (Bytes/Words) 000000xxx 256/128 Am49DL320BG (x16) Address Range 138000h–13FFFFh 140000h–147FFFh 148000h–14FFFFh 150000h–157FFFh 158000h–15FFFFh 160000h–167FFFh 168000h–16FFFFh 170000h–177FFFh 178000h– ...
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... SA44–SA47 SA48–SA51 SA52–SA55 SA56–SA59 SA60–SA62 SA63 SA64 SA65 SA66 SA67 SA68 SA69 SA70 Am49DL320BG Sector/ A20–A12 Sector Block Size 000000XXX 64 Kbytes 000001XXX, 000010XXX 192 (3x64) Kbytes 000011XXX 0001XXXXX 256 (4x64) Kbytes 0010XXXXX 256 (4x64) Kbytes ...
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... RESET# pin, all the previously pro- on the ID tected sectors are protected again. Figure 1 shows the algorithm, and Figure 25 shows the timing diagrams, for this feature. Am49DL320BG on the WP#/ACC pin, the de the WP#/ACC pin, the de- IH (11.5 V – 12.5 V). During this mode, ...
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... Perform Erase or Program Operations RESET Temporary Sector Unprotect Completed (Note 2) Notes: 1. All protected sectors unprotected (If WP#/ACC = V outermost boot sectors will remain protected). 2. All previously protected sectors are protected once again Am49DL320BG June 25, 2002 ...
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... Reset PLSCNT = 1 Increment PLSCNT No Yes PLSCNT = 1000? Yes Device failed Sector Unprotect Algorithm Am49DL320BG START PLSCNT = 1 RESET Wait First Write Temporary Sector Cycle = 60h? Unprotect Mode Yes No All sectors protected? Yes ...
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... Noise pulses of less than 5 ns (typical) on OE#, CE#f or WE# do not initiate a write cycle. Logical Inhibit Write cycles are inhibited by holding any one CE#f and WE# must be a logical zero while OE logical one. Am49DL320BG This IH ID power- the device does not ac- LKO CC is greater than V ...
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... Query Unique ASCII string “QRY” 0059h 0002h Primary OEM Command Set 0000h 0040h Address for Primary Extended Table 0000h 0000h Alternate OEM Command Set (00h = none exists) 0000h 0000h Address for Alternate OEM Extended Table (00h = none exists) 0000h Am49DL320BG Description 23 ...
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... Erase Block Region 2 Information 0000h 0001h 0000h 0000h Erase Block Region 3 Information 0000h 0000h 0000h 0000h Erase Block Region 4 Information 0000h 0000h Am49DL320BG Description pin present) PP pin present µs µ (00h = not supported (00h = not supported) ...
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... Not Supported Word Page Word Page ACC (Acceleration) Supply Minimum 0085h 00h = Not Supported, D7-D4: Volt, D3-D0: 100 mV ACC (Acceleration) Supply Maximum 0095h 00h = Not Supported, D7-D4: Volt, D3-D0: 100 mV Top/Bottom Boot Sector Flag 000Xh 02h = Bottom Boot Device, 03h = Top Boot Device Am49DL320BG Description 25 ...
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... The system must write the reset command to return to reading array data (or erase-suspend-read mode if the bank was previously in Erase Suspend). Enter SecSi Sector/Exit SecSi Sector Command Sequence The system can access the SecSi Sector region by is- suing the three-cycle Enter SecSi Sector command Am49DL320BG June 25, 2002 ...
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... In addition, the WP#/ACC pin must not be left floating or unconnected; inconsistent behavior of the device may result. Figure 3 illustrates the algorithm for the program oper- ation. Refer to the Erase and Program Operations table in the AC Characteristics section for parameters, and Figure 18 for timing diagrams. Am49DL320BG any operation HH 27 ...
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... Note that while the Embedded Erase operation is in progress, the system can read data from the non-erasing bank. The system can de- termine the status of the erase operation by reading Am49DL320BG June 25, 2002 ...
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... Command Sequence (Notes 1, 2) Data Poll to Erasing Bank from System No Data = FFh? Erasure Completed Notes: 1. See Tables 15 and 13 for erase command sequence. 2. See the section on DQ3 for information on the sector erase timer. Figure 4. Erase Operation Am49DL320BG START Embedded Erase algorithm in progress Yes 29 ...
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... The Erase Resume command is valid only during the Erase Suspend mode, and requires the bank address. 16. Command is valid when device is ready to read array data or when device is in autoselect mode. Am49DL320BG Fourth Fifth Data Addr Data ...
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... The Erase Resume command is valid only during the Erase Suspend mode, and requires the bank address. 16. Command is valid when device is ready to read array data or when device is in autoselect mode. Am49DL320BG Fourth Fifth Sixth Addr Data ...
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... During chip erase, a valid address is any non-protected sector address. 2. DQ7 should be rechecked even if DQ5 = “1” because DQ7 may change simultaneously with DQ5. Figure 5. Data# Polling Algorithm Am49DL320BG Yes No Yes Yes No ...
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... Reset Command Note: The system should recheck the toggle bit even if DQ5 = “1” because the toggle bit may stop toggling as DQ5 changes to “1.” See the subsections on DQ6 and DQ2 for more information. Figure 6. Toggle Bit Algorithm Am49DL320BG No Yes Yes Twice No ...
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... DQ3 prior to and following each subsequent sector erase com- mand. If DQ3 is high on the second status check, the last command might not have been accepted. Table 14 shows the status of DQ3 relative to the other status bits. Am49DL320BG June 25, 2002 ...
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... The device outputs array data if the system addresses a non-busy bank. June 25, 2002 Table 15. Write Operation Status DQ7 DQ6 (Note 2) (Note 1) DQ7# Toggle 0 Toggle 1 No toggle Data Data DQ7# Toggle Am49DL320BG DQ5 DQ2 DQ3 RY/BY# (Note 2) 0 N/A No toggle 0 1 Toggle 0 N/A Toggle Data Data Data ...
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... Operating ranges define those limits between which the func- tionality of the device is guaranteed –2 +2 +0.5 V 2.0 V Figure 8. Maximum Positive Am49DL320BG ) . . . . . . . . .–40°C to +85° Overshoot Waveform June 25, 2002 ...
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... min I = –100 µ min 4. Automatic sleep mode enables the low power mode when addresses remain stable for t current is 200 nA max Not 100% tested. Am49DL320BG Min Typ Max 1 0 ...
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... RC Cycle time = Min mA, 100% duty, IO CE1 CE2s = Min 1 –0 CE – 0.2 V, CE2 = V – 0.2 V CCS CCS CE2 = 0.2 V Am49DL320BG Min Typ Max Unit –1.0 1.0 µA or –1.0 1.0 µ 0 µA 5 µA –0.3 0.4 (Note 1) ...
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... Current vs. Time (Showing Active and Automatic Sleep Currents) CC1 Note June 25, 2002 1000 1500 2000 Time Frequency in MHz Figure 10. Typical I vs. Frequency CC1 Am49DL320BG 2500 3000 3500 3 4000 5 39 ...
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... Input Rise and Fall Times Input Pulse Levels Input timing measurement reference levels Output timing measurement reference levels INPUTS Steady Changing from Changing from Does Not Apply Center Line is High Impedance State (High Z) Measurement Level Am49DL320BG 70, 85 Unit 1 TTL gate 0.0–3 ...
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... AC CHARACTERISTICS CE#s Timing Parameter JEDEC Std Description — t CE#s Recover Time CCR E#f E1#s E2s Figure 13. Timing Diagram for Alternating June 25, 2002 — t CCR t CCR Between Pseudo SRAM to Flash Am49DL320BG Test Setup All Speeds Unit Min CCR t CCR 41 ...
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... Test Setup CE# Read Toggle and Data# Polling Addresses Stable t ACC OEH t CE HIGH Z Output Valid Figure 14. Read Operation Timings Am49DL320BG Speed 70 85 Unit Min 70 85 Max Max Max 30 40 Max 30 35 Max 30 ...
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... Description Max Max Min Min Min Min Ready Reset Timings NOT during Embedded Algorithms Reset Timings during Embedded Algorithms t Ready t RP Figure 15. Reset Timings Am49DL320BG All Speed Options Unit 20 s 500 ns 500 ...
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... Data Output (DQ7–DQ0) Address Input Output t FHQV The falling edge of the last WE# signal t SET ( HOLD AH and t specifications Am49DL320BG Speed 70 85 Unit Data Output (DQ7–DQ0) Address Input Data Output (DQ14–DQ0) DQ15 June 25, 2002 ...
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... Write Recovery Time from RY/BY Program/Erase Valid to RY/BY# Delay BUSY Notes: 1. Not 100% tested. 2. See the “Flash Erase And Programming Performance” section for more information. June 25, 2002 Byte Word Am49DL320BG Speed 70 85 Unit Min Min 0 ns ...
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... WPH A0h t BUSY is the true data at the program address. OUT Figure 18. Program Operation Timings Am49DL320BG Read Status Data (last two cycles WHWH1 D Status OUT VHH June 25, 2002 ...
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... These waveforms are for the word mode. Figure 20. Chip/Sector Erase Operation Timings June 25, 2002 SADD 555h for chip erase WPH t DH 55h 30h 10 for Chip Erase t BUSY Am49DL320BG Read Status Data WHWH2 In Complete Progress ...
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... OEH GHWL Valid Out t SR/W Read Cycle Complement Complement Status Data Status Data Am49DL320BG Valid PA Valid PA t CPH t CP Valid Valid In In CE#f Controlled Write Cycles VA High Z Valid Data True High Z True Valid Data June 25, 2002 ...
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... AHT AS t AHT t ASO t CEPH t OEPH t OE Valid Valid Status Status (first read) (second read) Enter Erase Suspend Program Erase Erase Suspend Suspend Read Program Figure 24. DQ2 vs. DQ6 Am49DL320BG Valid Valid Data Status (stops toggling) Erase Resume Erase Erase Complete Read 49 ...
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... VIDR CE#f WE# RY/BY# Figure 25. Temporary Sector Unprotect Timing Diagram Min Min Min Min Program or Erase Command Sequence t RSP Am49DL320BG All Speed Options Unit 500 ns 250 VIDR ...
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... For sector protect For sector unprotect SADD = Sector Address. Figure 26. Sector/Sector Block Protect and June 25, 2002 Valid* Valid* 60h Sector/Sector Block Protect: 150 µs, Sector/Sector Block Unprotect Unprotect Timing Diagram Am49DL320BG Valid* Verify 40h Status 51 ...
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... Word or Byte (Note Sector Erase Operation (Note 2) WHWH2 WHWH2 Notes: 1. Not 100% tested. 2. See the “Flash Erase And Programming Performance” section for more information Byte Word Am49DL320BG Speed 70 85 Unit Min Min 0 ns Min ...
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... SADD for sector erase 555 for chip erase Data# Polling GHEL t t WHWH1 CPH t BUSY for program PD for program 55 for erase 30 for sector erase 10 for chip erase is the data written to the device. OUT Am49DL320BG PA DQ7# D OUT 53 ...
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... ACC Indeterminate t OEE t COE 3. If CE#, LB#, or UB# goes low at the same time or after WE# goes low, the outputs will remain at high impedance. Figure 28. Psuedo SRAM Read Cycle Am49DL320BG Speed Unit ...
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... AOH OUT OUT COE Maximum 8 words Figure 29. Page Read Timing 3. If CE#, LB#, or UB# goes low at the same time or after WE# goes low, the outputs will remain at high impedance. Am49DL320BG Fixed High AOH OUT ...
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... Min 70 Min 50 Min 60 Min 60 Min Min Max Min Min Min Min ODW High Valid Data In Am49DL320BG Speed Unit 300 µ (Note 4) OEW t ...
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... If OE# is high during the write cycle, the outputs will remain at high impedance. Figure 31. Pseudo SRAM Write Cycle—CE1#s Control June 25, 2002 ODW t COE Valid Data In Am49DL320BG High-Z (Note 1) 57 ...
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... If OE# is high during the write cycle, the outputs will remain at high impedance COE t ODW Valid Data In Figure 32. Pseudo SRAM Write Cycle— UB#s and LB#s Control Am49DL320BG t WR High June 25, 2002 ...
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... V, 1,000,000 cycles 3.0 V, one pin at a time. CC Test Setup V V OUT V V Test Conditions Am49DL320BG Unit Comments sec Excludes 00h programming prior to erasure (Note 4) sec µs µs Excludes system level µs overhead (Note 5) sec , 1,000,000 cycles. Additionally, CC Min Max – ...
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... Test Setup CS1#s V – 0.2 V (Note 3.0 V, CE1 (Note 1) – 0.2 V (CE1#s controlled) or CE2s 0.2 V (CE2s controlled). t DPD Figure 33. Deep Power-down Timing t CHC t CH Figure 34. Power-on Timing Am49DL320BG Min Typ Max 2.7 3.3 – 0 (Note 2) 0 300 June 25, 2002 ...
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... RC min Figure 35. Read Address Skew min occur for a period greater than 10 µs, at least one valid address RC over min t WC min Figure 36. Write Address Skew min occur for a period greater than 10 µs, at least one valid address WC Am49DL320BG 61 ...
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... PHYSICAL DIMENSIONS FLB073—73-Ball Fine-Pitch Grid Array Am49DL320BG June 25, 2002 ...
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... AMD, the AMD logo, and combinations thereof are registered trademarks of Advanced Micro Devices, Inc. ExpressFlash is a trademark of Advanced Micro Devices, Inc. Product names used in this publication are for identification purposes only and may be trademarks of their respective companies. June 25, 2002 Am49DL320BG 63 ...