s72ns512pe0kjflg Meet Spansion Inc., s72ns512pe0kjflg Datasheet

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s72ns512pe0kjflg

Manufacturer Part Number
s72ns512pe0kjflg
Description
Mirrorbit Flash Memory And Dram
Manufacturer
Meet Spansion Inc.
Datasheet
S72NS-P Based MCPs/PoPs
MirrorBit
128/256/512 Mb (8/16/32 M x 16 bit), 1.8 Volt-only,
Multiplexed Simultaneous Read/Write, Burst Mode Flash
Memory
128/256 Mb (8/16 M x 16 bit) DDR DRAM on Split Bus
Data Sheet (Advance Information)
Notice to Readers: This document states the current technical specifications regarding the Spansion
product(s) described herein. Each product described herein may be designated as Advance Information,
Preliminary, or Full Production. See
Flash Memory and DRAM
Publication Number S72NS-P_00
Notice On Data Sheet Designations
Revision 01
Issue Date September 6, 2006
for definitions.
S72NS-P Based MCPs/PoPs Cover Sheet

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s72ns512pe0kjflg Summary of contents

Page 1

S72NS-P Based MCPs/PoPs ™ MirrorBit Flash Memory and DRAM 128/256/512 Mb (8/16/ bit), 1.8 Volt-only, Multiplexed Simultaneous Read/Write, Burst Mode Flash Memory 128/256 Mb (8/ bit) DDR DRAM on Split Bus Data Sheet (Advance ...

Page 2

Notice On Data Sheet Designations Spansion Inc. issues data sheets with Advance Information or Preliminary designations to advise readers of product information or intended specifications throughout the product life cycle, including development, qualification, initial production, and full production. In all ...

Page 3

S72NS-P Based MCPs/PoPs ™ MirrorBit Flash Memory and DRAM 128/256/512 Mb (8/16/ bit), 1.8 Volt-only, Multiplexed Simultaneous Read/Write, Burst Mode Flash Memory 128/256 Mb (8/ bit) DDR DRAM on Split Bus Data Sheet (Advance ...

Page 4

... S72NS256PD0KJFGC S72NS256PD0KJFLG S72NS256PD0KJFLC S72NS512PD0AJGGG S72NS512PD0AJGGC S72NS512PD0AJGLG S72NS512PD0AJGLC S72NS512PD0KJFGG S72NS512PD0KJFGC S72NS512PD0KJFLG S72NS512PD0KJFLC S72NS512PE0AJGGG S72NS512PE0AJGGC S72NS512PE0AJGLG S72NS512PE0AJGLC S72NS512PE0KJFGG S72NS512PE0KJFGC S72NS512PE0KJFLG S72NS512PE0KJFLC Flash DDR DRAM Flash Speed DDR DRAM Density Density (MHz) Speed (MHz 128 Mb ...

Page 5

Product Block Diagram F-RST# F-ACC F-WP# F-CE# F-OE# F-WE# AVD# F-V SS F2-CE# D-RAS# D-CAS# D-BA0 D-BA1 D-CKE D-WE# D-CE# D-Amax - D-A0 D-V CC D-V CCQ Notes: 1. Amax ...

Page 6

Connection Diagrams DNU DNU D-VSSQ B DNU D-VSS D-DQ13 C D-VCC D-DQ15 D-DQ14 D RFU A24 A22 A17 F A23 A19 A18 G F-CE# F-WP# F-WE# H F-ACC F-VCC F-CLK J A16 ...

Page 7

ADQ8 ADQ9 ADQ0 ADQ1 C F-AVD# F-OE# D F-RST# F-RDY E F-VCCQ F-WE# F F-VCCQ F-VSS G F-VSS F-VSS H F-VSS F-VSS ...

Page 8

Input/Output Descriptions Signal Amax – A16 ADQ15 – ADQ0 F-CE# F-OE# F-WE# F-VCC F-VCCQ F-VSS F-RDY F-CLK F-AVD# F-RST# F-WP# F-ACC D-A12 – D-A0 D-DQ15 – D-DQ0 D-CLK D-CE# D-CKE D-BA1 – BA0 D-RAS# D-CAS# D-UDQM – D-LDQM D-WE# ...

Page 9

Ordering Information The order number (Valid Combination) is formed by the following: S72NS 256 Code Flash Product Density Process Family (Mb) Technology 128 S72NS 256 512 ...

Page 10

Physical Dimensions 6.1 NLC133—133-ball Fine-Pitch Ball Grid Array (FBGA) 11.0 x 10.0 mm PACKAGE NLC 133 JEDEC N 11 10.00 mm PACKAGE SYMBOL MIN NOM A 0.90 1.00 A1 0.20 0.25 A2 0.70 0.76 ...

Page 11

6.2 NSC133—133-ball Fine-Pitch Ball Grid Array (FBGA) 8.0 x 8.0 mm PACKAGE NSC 133 JEDEC N 8. 8.00 mm PACKAGE SYMBOL MIN NOM A 0.90 1.00 ...

Page 12

ALJ128—128-ball Fine-Pitch Ball Grid Array (FBGA) 12.0 x 12.0 mm PIN A1 CORNER INDEX MARK 0.10 C (2X 128X 0. 0. PACKAGE ALJ 128 JEDEC N ...

Page 13

6.4 ASF128—128-ball Fine-Pitch Ball Grid Array (FBGA) 12.0 x 12.0 mm PACKAGE ASF128 JEDEC 12. 12.00 mm PACKAGE SYMBOL MIN NOM A 0.95 A1 0.35 A2 ...

Page 14

Revision History 7.1 Revision 01 (September 6, 2006) Initial release. Colophon The products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and ...

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