lrs1338a Sharp Microelectronics of the Americas, lrs1338a Datasheet
lrs1338a
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lrs1338a Summary of contents
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... Total standby current is the summation of flash’s memory standby current and SRAM’s one. DESCRIPTION The LRS1338A is a combination memory organized as 524,288 × 16-bit flash memory and 262,144 × 8-bit static RAM in one package fabricated using silicon- gate CMOS process technology. ...
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... S-A 0 262,144 x 8 BIT S-CE SRAM S-OE S-WE S-V CC Figure 2. LRS1338A Block Diagram Table 1. Pin Descriptions DESCRIPTION 17 Common Address Input Pins 16 Address Input Pin for SRAM Address Input Pin for Flash Memory 18 Chip Enable Input Pin for Flash Memory Chip Enable Input Pin for SRAM ...
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... V PPH V , memory con- T < -30°C produce spurious results and should not be attempted. PPLK A 7. Refer to Table 6 for valid D LRS1338A = open (HIGH-Z). RP needs open 0 open (HIGH-Z). ...
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... LRS1338A ABSOLUTE MAXIMUM RATINGS PARAMETER SYMBOL Supply voltage V Input voltage Operating temperature T Storage temperature T V voltage V PP Input voltage NOTES: 1. The maximum applicable voltage on any pins with respect to GND. 2. Except Except RP. 4. -2.0 V undershoot is allowed when the pulse width is less than 20 ns. ...
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... This value is standby current (I 7. This value is deep power down current (I flash memory flash memory. 8. This value is standby current (I PPW ) of flash memory. 9. This value is standby current (I 10. Reference values at V LRS1338A MIN. TYP. MAX. UNIT NOTES -1.5 1.5 µA or -1.5 1.5 µ ...
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... PP • Allow V connection to 3 Product Overview The LRS1338A is a high-performance 8M Smart- Voltage flash memory organized as 512K-word of 16 bits. The 512K-word of data is arranged in two 4K-word boot blocks, six 4K-word parameter blocks and fifteen 32K-word main blocks which are individually erasable in-system. The memory map is shown in Figure 4. ...
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... ADDRESS COUNTER Data Sheet I INPUT BUFFER DATA REGISTER IDENTIFIER REGISTER COMMAND STATUS REGISTER REGISTER DATA COMPARATOR MACHINE Y GATING Figure 3. Flash Memory Block Diagram LRS1338A I/O V LOGIC USER RP WP WRITE PROGRAM/ERASE STATE VOLTAGE SWITCH 15 32K-WORD BLOCKS . . . GND LRS1338A-3 7 ...
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... LRS1338A SYMBOL TYPE ADDRESS INPUTS: Inputs for addresses during read and write operations Input 0 18 Addresses are internally latched during the write cycle. DATA INPUT/OUTPUTS: Inputs data and commands during CUI write cycles; out- puts data during memory array, status register, and identifier code read cycles. Data ...
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... MAIN BLOCK 2 32K-WORD MAIN BLOCK 3 32K-WORD MAIN BLOCK 4 32K-WORD MAIN BLOCK 5 32K-WORD MAIN BLOCK 6 32K-WORD MAIN BLOCK 7 32K-WORD MAIN BLOCK 8 32K-WORD MAIN BLOCK 9 32K-WORD MAIN BLOCK 10 32K-WORD MAIN BLOCK 11 32K-WORD MAIN BLOCK 12 32K-WORD MAIN BLOCK 13 32K-WORD MAIN BLOCK 14 LRS1338A-4 Figure 4. Memory Map 9 ...
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... LRS1338A Bus Operation The local CPU reads and writes flash memory in- system. All bus cycles to or from the flash memory con- form to standard microprocessor bus cycles. READ Information can be read from any block, identifier codes or status register independent of the V age. RP can be either ...
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... FIRST BUS CYCLE OPER. ADDR. DATA Write X FFH Write X 90H Write X 70H Write X 50H Write BA 20H Write WA 40H or 10H Write X B0H Write X D0H . IH LRS1338A V I/O - I/O NOTES OUT X X HIGH HIGH HIGH and PPH CC CC1 ...
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... LRS1338A READ ARRAY COMMAND Upon initial device power-up and after exit from deep power-down mode, the device defaults to read array mode. This operation is also initiated by writing the Read Array command. The device remains enabled for reads until another command is written. Once the internal WSM has started a block erase or ...
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... Addr = Within Block to be Erased Erase Data = D0H Addr = Within Block to be Erased Status Register Data Check SR WSM Ready 0 = WSM Busy COMMENTS Check SR Error Detect PP Check SR Device Protect Detect Check SR.4, 5 Both 1 = Command Sequence Error Check SR Block Erase Error LRS1338A LRS1338A-6 13 ...
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... LRS1338A WORD WRITE COMMAND Word write is executed by a two-cycle command sequence. Word write setup (standard 40H or alternate 10H) is written, followed by a second write that speci- fies the address and data (latched on the rising edge of WE). The WSM then takes over, controlling the word write and write verify algorithms internally ...
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... LRS1338A COMMENTS Data = 40H or 10H Addr = Location to be Written Data = Data to be Written Addr = Location to be Written Status Register Data Check SR WSM Ready 0 = WSM Busy COMMENTS Check SR Error Detect PP Check SR Device Protect Detect Check SR Data Write Error LRS1338A-7 15 ...
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... Erase Completed Write FFH Read Array Data Stacked Chip (8M Flash & 2M SRAM) COMMENTS Erase Data = B0H Suspend Addr = X Status Register Data Addr = X Check SR WSM Ready 0 = WSM Busy Check SR Block Erase Suspended 0 = Block Erase Completed Data = D0H Erase Addr = X Resume LRS1338A-8 Data Sheet ...
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... COMMENTS Data = B0H Addr = X Status Register Data Addr = X Check SR WSM Ready 0 = WSM Busy Check SR Word Write Suspended 0 = Word Write Completed Data = FFH Read Addr = X Array Read Array locations other than that being written Data = D0H Addr = X PP LRS1338A-9 17 ...
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... LRS1338A OPERATION Word Write or Block Erase WSMS ESS 7 6 SR.7 = Write State Machine Status (WSMS Ready 0 = Busy SR.6 = Erase Suspend Status (ESS Block Erase Suspended 0 = Block Erase in Progress/Completed SR.5 = Erase( Error in Block Erasure 0 = Successful Block Erase SR.4 = Word Write (WWS Error in Word Write 0 = Successful Word Write SR ...
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... RP is first raised Characteristics — Read Only and Write Operations’ and Figure 12, 13 and 14 for more information. LRS1338A during block erase transitions LKO , the CUI must be placed in read PPLK powers-up first ...
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... TEST CONFIGURATION Stacked Chip (8M Flash & 2M SRAM) 1.35 TEST POINTS = 2 3 1.3 V 1N914 DEVICE UNDER OUT TEST C L Includes Jig Capacitance Figure 11. Transient Equivalent Testing Load Circuit Table 10. Test Configuration Capacitance Loading Value C (pF Data Sheet OUTPUT LRS1338A-10 LRS1338A-11 ...
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... Block erases and word writes are inhibited when the correspond ing CCR IH are not guaranteed with V should not be attempted connection lative period of 80 hours respectively. CCW LRS1338A TEST CONDITIONS = V MAX GND MAX., V ...
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... IL t AVEL IL t GLQV IL t ELQV t GLQX t ELQX HIGH Z VALID OUTPUT t AVQV t PHQV IL Stacked Chip (8M Flash & 2M SRAM) MAX. UNIT NOTES ns 120 ns 120 ns 2 600 ELQV t EHQZ t GHQZ t OH HIGH Z LRS1338A-12 Data Sheet ...
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... RP should be held PPH determination of block erase or word write success (SR.1, SR.3, SR.4, SR.5 = 0). Data Sheet 1 MIN. MAX. UNIT NOTES 120 ns 1 µ 100 ns 100 ns 100 until HH LRS1338A ...
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... WHOV1 WLWH t DVWH t WHDX V HIGH PHWL SHWH PHHWH VPWH V PPH PPLK V IL Stacked Chip (8M Flash & 2M SRAM VALID SRD QVSL t QVPH t QVVL LRS1338A-13 Data Sheet ...
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... RP should be held PPH determination of block erase or word write success (SR.1, SR.3, SR.4, SR.5 = 0). Data Sheet 1 MIN. MAX. UNIT 120 ns 1 µ 100 ns 100 ns 100 until HH LRS1338A NOTES ...
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... EHQV1 ELEH t DVEH t EHDX V HIGH PHEL EHEH PHHEH VPEH V PPH PPLK V IL Stacked Chip (8M Flash & 2M SRAM VALID SRD QVSL t QVPH t QVVL LRS1338A-14 Data Sheet ...
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... PLPH A. Reset during Block Erase or Word Write or Read Array Mode t VPH B. RP rising Timing Table 11. Reset AC Specifications MIN 100 100 2 3 MIN. LRS1338A LRS1338A-15 UNIT NOTES MAX UNIT NOTES 2 MAX. TYP. 44.6 µs 45.9 µs 1.46 sec 0.19 sec 1 ...
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... LRS1338A SRAM* Description The LRS1388A bit static RAM organized as 262,144 × 8 bit which provides low-power standby mode. Features • Access Time (MAX.) • Operating Current: – (MAX.) – (MAX NOTE Don’t care, L= LOW HIGH. ...
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... CONTROL LOGIC OE CONTROL OE LOGIC Data Sheet 10 1024 ROW MEMORY CELL ARRAY DECODER 8 COLUMN 256 DECODER I/O BUFFER I/O I/O I/O I/O I Figure 16. SRAM Block Diagram LRS1338A V CC (1024 x 256 x 8) GND 256 x 8 COLUMN GATE 8 I/O I/O I LRS1338A-16 29 ...
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... LRS1338A SRAM Absolute Maximum Ratings PARAMETER SYMBOL Supply voltage V Input voltage Operating temperature T Storage temperature T NOTES: 1. The maximum applicable voltage on any pins with respect to GND. 2. -2.0 V undershoot is allowed when the pulse width is less than 20 ns. SRAM Recommended DC Operating Conditions T = -40°C to +85°C ...
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... OHZ SYMBOL CONDITIONS 0.2 V CCDR CCDR CCDR CE V – 0 CCDR CCDR CCDR CCDR t CDR t R LRS1338A MAX. UNIT MAX. UNIT MIN ...
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... LRS1338A Timing Diagrams ADDRESS OUT NOTE HIGH for Read Cycle ACE OLZ Data Valid Figure 17. Read Cycle Timing Diagram Stacked Chip (8M Flash & 2M SRAM OHZ t OH 1338A-17 Data Sheet ...
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... If CE goes HIGH simultaneously with WE going HIGH or before WE going HIGH, the outputs remain in HIGH impedance state. Figure 18. Write Cycle Timing Diagram (OE Controlled) Data Sheet CWP (NOTE (NOTE 3) (NOTE 1) t OHZ t DW (NOTE 5) applies WR LRS1338A t WR (NOTE (NOTE Data Valid 1338A-18 33 ...
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... LRS1338A ADDRESS OUT D IN NOTES measured from the later of CE going LOW to the end of write measured from the address valid to the beginning of write measured from the end of write to the address change case a write ends going HIGH. ...
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... Stacked Chip (8M Flash & 2M SRAM) OUTLINE DIMENSIONS 48TSOP (TSOP48-P-1014 NOTE: Dimensions are in mm. Data Sheet 0.3 14.0 0.2 12.4 13.0 0.3 LRS1338A 48 25 48TSOP2 35 ...
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... LRS1338A LIFE SUPPORT POLICY SHARP components should not be used in medical devices with life support functions or in safety equipment (or similiar applications where component failure would result in loss of life or physical harm) without the written approval of an officer of the SHARP Corporation. LIMITED WARRANTY SHARP warrants to its Customer that the Products will be free from defects in material and workmanship under normal use and service for a period of one year from the date of invoice ...