k4t1g084qc Samsung Semiconductor, Inc., k4t1g084qc Datasheet - Page 20

• Manufacturer Part Number: k4t1g084qc
• Description: 1gb C-die Ddr2 Sdram Specification
• Manufacturer: Samsung Semiconductor, Inc.

14.0 General notes, which may apply for all AC parameters
1. Slew Rate Measurement Levels
2. DDR2 SDRAM AC timing reference load
representation of the typical system environment or a depiction of the actual load presented by a production tester. System designers will use IBIS or
other simulation tools to correlate the timing reference load to a system environment. Manufacturers will correlate to their production test conditions (gen-
erally a coaxial transmission line terminated at the tester electronics).
The output timing reference voltage level for single ended signals is the crosspoint with VTT. The output timing reference voltage level for differential sig-
nals is the crosspoint of the true (e.g. DQS) and the complement (e.g. DQS) signal.
3. DDR2 SDRAM output slew rate test load
K4T1G044QC
K4T1G084QC
Following figure represents the timing reference load used in defining the relevant timing parameters of the part. It is not intended to be either a precise
a. Output slew rate for falling and rising edges is measured between VTT - 250 mV and VTT + 250 mV for single ended signals.
b. Input slew rate for single ended signals is measured from dc-level to ac-level: from VIL(dc) to VIH(ac) for rising edges and from VIH(dc) and VIL(ac)
c. VID is the magnitude of the difference between the input voltage on CK and the input voltage on CK, or between DQS and DQS for differential
Output slew rate is characterized under the test conditions as shown in the following figure.
For differential signals (e.g. DQS - DQS) output slew rate is measured between DQS - DQS = -500 mV and DQS - DQS = +500mV.
Output slew rate is guaranteed by design, but is not necessarily tested on each device.
for falling edges.
strobe.
For differential signals (e.g. CK - CK) slew rate for rising edges is measured from CK - CK = -250 mV to CK - CK = +500 mV (250mV to -500 mV
for falling edges).
VDDQ
VDDQ
DUT
DUT
RDQS, RDQS
DQS, DQS
RDQS
RDQS
DQS
DQS
DQ
DQ
<AC Timing Reference Load>
Output
Output
<Slew Rate Test Load>
Test point
Timing
reference
point
20 of 26
25
25
Ω
Ω
V
V
TT
TT
= V
= V
DDQ
DDQ
/2
/2
DDR2 SDRAM
Rev. 1.1 June 2007