k4s560432a Samsung Semiconductor, Inc., k4s560432a Datasheet - Page 2

• Manufacturer Part Number: k4s560432a
• Description: 256mbit Sdram 16m X 4bit X 4 Banks Synchronous Dram Lvttl
• Manufacturer: Samsung Semiconductor, Inc.

K4S560432A
16M x 4Bit x 4 Banks Synchronous DRAM
FEATURES
• JEDEC standard 3.3V power supply
• LVTTL compatible with multiplexed address
• Four banks operation
• MRS cycle with address key programs
• All inputs are sampled at the positive going edge of the system
• Burst read single-bit write operation
• DQM for masking
• Auto & self refresh
• 64ms refresh period (8K cycle)
FUNCTIONAL BLOCK DIAGRAM
clock.
-. CAS latency (2 & 3)
-. Burst length (1, 2, 4, 8 & Full page)
-. Burst type (Sequential & Interleave)
ADD
CLK
LCKE
CLK
* Samsung Electronics reserves the right to change products or specification without notice.
LRAS
CKE
Bank Select
LCBR
CS
LWE
RAS
Timing Register
LCAS
CAS
GENERAL DESCRIPTION
rate Dynamic RAM organized as 4 x 16,785,216 words by 4 bits,
fabricated with SAMSUNG's high performance CMOS technol-
ogy. Synchronous design allows precise cycle control with the use
of system clock I/O transactions are possible on every clock cycle.
Range of operating frequencies, programmable burst length and
programmable latencies allow the same device to be useful for a
variety of high bandwidth, high performance memory system
applications.
ORDERING INFORMATION
K4S560432A-TC/L75
K4S560432A-TC/L80
K4S560432A-TC/L1H
K4S560432A-TC/L1L
Latency & Burst Length
The K4S560432A is 268,435,456 bits synchronous high data
Programming Register
WE
Data Input Register
Column Decoder
16M x 4
16M x 4
16M x 4
16M x 4
Part No.
DQM
LWCBR
133MHz(CL=3)
125MHz(CL=3)
100MHz(CL=2)
100MHz(CL=3)
Max Freq.
Rev. 0.0 Sep. 1999
CMOS SDRAM
LDQM
Interface Package
LVTTL
LWE
LDQM
DQi
TSOP(II)
54pin