ic42s16160 ETC-unknow, ic42s16160 Datasheet - Page 20

• Manufacturer Part Number: ic42s16160
• Description: 4m X 16bit X 4 Banks 256-mbit Sdram
• Manufacturer: ETC-unknow

IC42S16160
Precharge
The precharge command can be asserted anytime after t
Soon after the precharge command is asserted, the precharge operation is performed and the synchronous DRAM enters
the idle state after t
The earliest timing in a read cycle that a precharge command can be asserted without losing any data in the burst is as
follows.
In order to write all data to the memory cell correctly, the asynchronous parameter t
specification defines the earliest time that a precharge command can be asserted. The minimum number of clocks can be
calculated by dividing t
In summary, the precharge command can be asserted relative to the reference clock that indicates the last data word is
valid. In the following table, minus means clocks before the reference; plus means time after the reference.
20
PrechargeE
CAS latency = 2
Command
DQ
CLK
Command
CAS latency = 3
DQ
RP
(min.) is satisfied. The parameter t
DPL
(min.) with the clock cycle time.
CAS
CAS
CAS
CAS
CAS latency
T0
Read
Read
2
3
T1
Read
T2
RP
-1
-2
RAS
is the time required to perform the precharge.
Q0
(min.) is satisfied.
T3
+ t
+ t
Q0
Q1
DPL
DPL
Write
((min.)
((min.)
T4
Q1
PRE
PRE
Q2
DPL
T5
Integrated Circuit Solution Inc.
must be satisfied. The t
Q2
Q3
T6
(t
Q3
RAS
Hi - Z
is satisfied)
T7
Burst lengh=4
Hi - Z
DR037-0A 9/05/2003
DPL
(min.)