mt18htf25672pdz Micron Semiconductor Products, mt18htf25672pdz Datasheet - Page 4

• Manufacturer Part Number: mt18htf25672pdz
• Description: 2gb X72, Ecc, Dr 240-pin Ddr2 Sdram Rdimm
• Manufacturer: Micron Semiconductor Products

Table 5:
PDF: 09005aef83d3d893/Source: 09005aef83d3d8c1
htf18c256x72pdz.fm - Rev. A 11/09 EN
RAS#, CAS#,
DQS#[17:9]
CK0, CK0#
DQS[17:9]
DQS#[8:0]
V
DQS[8:0],
ODT[1:0]
DQ[63:0]
Symbol
CKE[1:0]
DM[8:0]
Err_Out
A[15:0]
BA[2:0]
RESET#
SA[2:0]
CB[7:0]
DD
V
S#[1:0]
Par_In
WE#
SDA
DDSPD
V
SCL
V
NC
/V
REF
SS
DDQ
Pin Descriptions
(open drain)
(SSTL_18)
(SSTL_18)
(SSTL_18)
(SSTL_18)
(SSTL_18)
(SSTL_18)
(SSTL_18)
(SSTL_18)
(SSTL_18)
(SSTL_18)
Output
Supply
Supply
Supply
Supply
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Type
I/O
I/O
I/O
I/O
–
Description
Address inputs: Provide the row address for ACTIVE commands, and the column address
and auto precharge bit (A10) for READ/WRITE commands, to select one location out of the
memory array in the respective bank. A10 sampled during a PRECHARGE command
determines whether the PRECHARGE applies to one device bank (A10 LOW, device bank
selected by BA[2/1:0]) or all device banks (A10 HIGH). The address inputs also provide the
op-code during a LOAD MODE command. A[13:0] (2GB). A[15:14] are connected for parity.
Bank address inputs: BA[2:0] define the device bank to which an ACTIVE, READ, WRITE,
or PRECHARGE command is being applied. BA[2:0] define which mode register (MR, EMR1,
EMR2, and EMR3) is loaded during the LOAD MODE command.
Clock: CK and CK# are differential clock inputs. All control, command, and address input
signals are sampled on the crossing of the positive edge of CK and the negative edge of
CK#.
Clock enable: CKE enables (registered HIGH) and disables (registered LOW) internal
circuitry and clocks on the DDR2 SDRAM.
Input data mask: DM is an input mask signal for write data. Input data is masked when
DM is sampled HIGH, along with the input data, during a write access. DM is sampled on
both edges of DQS. Although the DM pins are input-only, DM loading is designed to match
that of the DQ and DQS pins. If RDQS is disabled, RDQS[17:9] become DM[8:0] and
RDQS#[17:9] are no function.
On-die termination: ODT enables (registered HIGH) and disables (registered LOW)
termination resistance internal to the DDR2 SDRAM. When enabled in normal operation,
ODT is only applied to the following pins: DQ, DQS, DQS#, DM, and CB. The ODT input will
be ignored if disabled via the LOAD MODE command.
Parity input: Parity bit for the address, RAS#, CAS#, and WE#.
Command inputs: RAS#, CAS#, and WE# (along with S#) define the command being
entered.
Reset: Asynchronously forces all registered outputs LOW when RESET# is LOW. This signal
can be used during power-up to ensure that CKE is LOW and DQ are High-Z.
Chip select: S# enables (registered LOW) and disables (registered HIGH) the command
decoder.
Serial address inputs: These pins are used to configure the SPD EEPROM address range
on the I
Serial clock for SPD EEPROM: SCL is used to synchronize communication to and from the
SPD EEPROM.
Check bits.
Data input/output: Bidirectional data bus.
Data strobe: Output with read data. Edge-aligned with read data. Input with write data.
Center-aligned with write data. DQS# is only used when differential data strobe mode is
enabled via the LOAD MODE command.
Serial data: SDA is a bidirectional pin used to transfer addresses and data into and out of
the SPD EEPROM on the I
Parity error output: Parity error found on the command and address bus.
Power supply: 1.8V ±0.1V. The component V
V
SPD EEPROM power supply: +1.7V to +3.6V.
Reference voltage: V
Ground.
No connect: These pins are not connected on the module.
DD
.
2
C bus.
2GB (x72, ECC, DR) 240-Pin DDR2 SDRAM RDIMM
DD
2
/2.
C bus.
4
Micron Technology, Inc., reserves the right to change products or specifications without notice.
Pin Assignments and Descriptions
DD
and V
DDQ
are connected to the module
©2009 Micron Technology, Inc. All rights reserved.