mt18hvf12872py-53e Micron Semiconductor Products, mt18hvf12872py-53e Datasheet - Page 8

• Manufacturer Part Number: mt18hvf12872py-53e
• Description: 1gb X72, Ecc, Sr 240-pin Ddr2 Sdram Vlp Rdimm
• Manufacturer: Micron Semiconductor Products

I
Table 8:
PDF: 09005aef82255aba/Source: 09005aef81c753af
HVF18C128x72.fm - Rev. C 3/07 EN
Parameter/Condition
Operating one bank active-precharge current:
t
commands; Address bus inputs are switching; Data bus inputs are switching
Operating one bank active-read-precharge current: I
BL = 4, CL = CL (I
t
inputs are switching; Data pattern is same as I
Precharge power-down current: All device banks idle;
LOW; Other control and address bus inputs are stable; Data bus inputs are
floating
Precharge quiet standby current: All device banks idle;
HIGH, S# is HIGH; Other control and address bus inputs are stable; Data bus
inputs are floating
Precharge standby current: All device banks idle;
S# is HIGH; Other control and address bus inputs are switching; Data bus inputs
are switching
Active power-down current: All device banks open;
t
inputs are stable; Data bus inputs are floating
Active standby current: All device banks open;
t
commands; Other control and address bus inputs are switching; Data bus inputs
are switching
Operating burst write current: All device banks open; Continuous burst
writes; BL = 4, CL = CL (I
t
inputs are switching; Data bus inputs are switching
Operating burst read current: All device banks open; Continuous burst reads;
I
t
inputs are switching; Data bus inputs are switching
Burst refresh current:
t
control and address bus inputs are switching; Data bus inputs are switching
Self refresh current: CK and CK# at 0V; CKE ≤ 0.2V; Other control and address
bus inputs are floating; Data bus inputs are floating
Operating bank interleave read current: All device banks interleaving reads;
I
t
between valid commands; Address bus inputs are stable during DESELECTs; Data
bus inputs are switching
DD
OUT
OUT
RC =
RCD =
CK =
RAS =
RP =
RP =
RFC (I
RC =
= 0mA; BL = 4, CL = CL (I
Specifications
= 0mA; BL = 4, CL = CL (I
t
t
t
t
t
RP (I
RP (I
DD
RC (I
RC (I
CK (I
t
t
RAS MAX (I
RCD (I
) interval; CKE is HIGH, S# is HIGH between valid commands; Other
DD
DD
DD
DD
DD
); CKE is HIGH, S# is HIGH between valid commands; Address bus
); CKE is HIGH, S# is HIGH between valid commands; Address bus
),
),
DDR2 I
Values shown for MT47H128M4 DDR2 SDRAM only and are computed from values specified in the
512Mb (128 Meg x 4) component data sheet
); CKE is LOW; Other control and address bus
DD
t
t
RAS =
DD
RRD =
); CKE is HIGH, S# is HIGH between valid commands; Address bus
), AL = 0;
DD
),
DD
t
t
RAS MIN (I
RRD (I
t
DD
RP =
t
CK =
Specifications and Conditions – 1GB
), AL = 0;
t
DD
CK =
DD
t
DD
RP (I
t
), AL =
CK (I
), AL = 0;
),
t
DD
t
CK (I
DD
RCD =
t
DD
); CKE is HIGH, S# is HIGH between valid
CK =
); CKE is HIGH, S# is HIGH between valid
t
); REFRESH command at every
RCD (I
DD
t
t
),
t
CK =
RCD (I
CK (I
t
RC =
DD
DD
t
DD
) - 1 x
CK (I
DD
4W
1GB (x72, ECC, SR) 240-Pin DDR2 SDRAM VLP RDIMM
t
),
RC (I
t
CK =
); CKE is HIGH, S# is HIGH
t
t
RAS =
DD
CK =
t
CK =
t
CK (I
DD
),
t
CK (I
t
),
RAS =
t
t
OUT
CK (I
CK =
t
t
t
DD
t
CK (I
RAS MAX (I
RAS =
CK =
8
DD
);
= 0mA;
DD
t
t
),
DD
Fast PDN exit
MR[12] = 0
Slow PDN exit
MR[12] = 1
t
CK =
CK (I
RAS MAX (I
t
),
CK (I
t
); CKE is HIGH,
RAS MIN (I
DD
t
CK (I
Micron Technology, Inc., reserves the right to change products or specifications without notice.
DD
DD
); CKE is
); CKE is
),
DD
DD
),
DD
),
),
Symbol
I
I
I
I
I
I
I
DD
DD
DD
DD
I
I
DD
DD
DD
I
I
I
DD
DD
DD
DD
DD
4W
2Q
2N
3N
2P
3P
4R
0
1
5
6
7
Electrical Specifications
1,620 1,440 1,440
1,890 1,710 1,620
1,170
3,060 2,520 2,070
3,240 2,610 2,070
3,240 3,060 2,970
4,320 4,050 3,960
-667
126
810
900
630
216
126
©2003 Micron Technology, Inc. All rights reserved.
-53E
126
720
810
540
216
990
126
-40E
810
126
630
720
450
216
126
Units
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA