mt18hvs25672pky-53e Micron Semiconductor Products, mt18hvs25672pky-53e Datasheet - Page 9

• Manufacturer Part Number: mt18hvs25672pky-53e
• Description: 2gb, 4gb X72, Dr 244-pin Ddr2 Vlp Mini-rdimm
• Manufacturer: Micron Semiconductor Products

I
Table 8:
PDF: 09005aef8281e0a3/Source: 09005aef8281d7ea
HVS18C256_512x72PK.fm - Rev. A 8/07 EN
Parameter/Condition
Operating one bank active-precharge current:
t
commands; Address bus inputs are switching; Data bus inputs are switching
Operating one bank active-read-precharge current: I
CL = CL (I
t
bus inputs are switching; Data pattern is same as I
Precharge power-down current: All device banks idle;
is LOW; Other control and address bus inputs are stable; Data bus inputs are
floating
Precharge quiet standby current: All device banks idle;
CKE is HIGH, S# is HIGH; Other control and address bus inputs are stable; Data
bus inputs are floating
Precharge standby current: All device banks idle;
HIGH, S# is HIGH; Other control and address bus inputs are switching; Data
bus inputs are switching
Active power-down current: All device banks open;
inputs are stable; Data bus inputs are floating
Active standby current: All device banks open;
t
commands; Other control and address bus inputs are switching; Data bus
inputs are switching
Operating burst write current: All device banks open, continuous burst
writes; BL = 4, CL = CL (I
t
inputs are switching; Data bus inputs are switching
Operating burst read current: All device banks open, continuous burst
reads; I
t
commands; Address bus inputs are switching; Data bus inputs are switching
Burst refresh current:
interval; CKE is HIGH, S# is HIGH between valid commands; Other control and
address bus inputs are switching; Data bus inputs are switching
Self refresh current: CK and CK# at 0V; CKE ≤ 0.2V; Other control and
address bus inputs are floating; Data bus inputs are floating
Operating bank interleave read current: All device banks interleaving
reads; I
t
HIGH, S# is HIGH between valid commands; Address bus inputs are stable
during deselects; Data bus inputs are switching
DD
RC =
RCD =
t
RAS =
RP =
RAS =
CK =
CK =
Specifications
t
t
t
RP (I
RC (I
t
CK (I
t
t
CK (I
OUT
OUT
t
RAS MAX (I
RAS MAX (I
RCD (I
DD
DD
= 0mA; BL = 4, CL = CL (I
DD
DD
= 0mA; BL = 4, CL = CL (I
), AL = 0;
DD
); CKE is HIGH, S# is HIGH between valid commands; Address bus
),
),
I
Values are shown for the MT47H256M8THN DDR2 SDRAM only and are computed from values specified in
the 2Gb TwinDie (256 Meg x 8) component data sheet
DD
); CKE is LOW; Other control and address bus
DD
t
t
RAS =
RC =
); CKE is HIGH, S# is HIGH between valid commands; Address
Specifications and Conditions – 2GB
DD
DD
t
t
CK =
),
),
RC (I
t
RAS MIN (I
t
DD
t
t
RP =
RP =
CK =
), AL = 0;
DD
t
CK (I
),
t
t
t
RP (I
RP (I
CK (I
t
RRD =
DD
DD
DD
DD
),
DD
DD
DD
t
); CKE is HIGH, S# is HIGH between valid
CK =
t
); CKE is HIGH, S# is HIGH between valid
); CKE is HIGH, S# is HIGH between valid
RC =
), AL =
); REFRESH command at every
), AL = 0;
t
RRD (I
t
CK (I
t
RC (I
t
RCD (I
DD
DD
t
),
DD
CK =
),
t
t
DD
),
RCD =
CK =
DD
t
t
RAS =
CK =
t
t
4W
2GB, 4GB (x72, DR) 244-Pin DDR2 VLP Mini-RDIMM
RAS =
CK =
t
) - 1 ×
CK (I
t
CK (I
t
t
t
RCD (I
OUT
CK =
CK (I
t
t
DD
t
CK (I
RAS MAX (I
t
CK =
RAS MIN (I
t
CK (I
9
DD
),
= 0mA; BL = 4,
Fast PDN exit
MR[12] = 0
Slow PDN exit
MR[12] = 1
DD
t
DD
),
DD
CK (I
t
),
DD
CK (I
); CKE is
); CKE is
t
);
RFC (I
DD
DD
Micron Technology, Inc., reserves the right to change products or specifications without notice.
DD
DD
); CKE
);
),
),
DD
)
Symbol
I
I
I
I
I
I
I
CDD
CDD
CDD
CDD
I
I
CDD
CDD
CDD
I
I
I
CDD
CDD
CDD
CDD
CDD
4W
2Q
2N
3N
4R
2P
3P
0
1
5
6
7
Electrical Specifications
1,098
1,548
1,548
2,223
3,123
-80E
918
126
513
558
333
153
648
126
©2007 Micron Technology, Inc. All rights reserved.
1,008
1,323
1,323
2,043
2,628
-667
873
126
423
468
333
153
603
126
1,233
1,233
1,998
2,538
-53E
738
963
126
423
468
333
153
513
126
Units
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA