mt18vddt12872 Micron Semiconductor Products, mt18vddt12872 Datasheet - Page 25

• Manufacturer Part Number: mt18vddt12872
• Description: 256mb, 512mb, 1gb, 2gb X72, Ecc, Sr 184-pin Ddr Sdram Rdimm
• Manufacturer: Micron Semiconductor Products

pdf: 09005aef808a331f, source: 09005aef80858037
DD18C32_64_128_256x72G.fm - Rev. E 9/04 EN
43. Random address changing and 100 percent of
44. CKE must be active (high) during the entire time a
45. I
data changing at every transfer.
refresh command is executed. That is, from the
time the AUTO REFRESH command is registered,
CKE must be active at each rising clock edge, until
t
driven to a valid high or low logic level. I
similar to I
address and control inputs to remain stable.
Although I
I
REF later.
DD
DD
2N specifies the DQ, DQS, and DM to be
2
F
is “worst case.”
DD
DD
2
F
2
, I
F
DD
except I
2
N
, and I
DD
DD
2Q specifies the
2Q are similar,
DD
256MB, 512MB, 1GB, 2GB (x72, ECC, SR)
2Q is
25
46. Whenever the operating frequency is altered, not
47. Leakage number reflects the worst case leakage
48. When an input signal is indicated to be HIGH or
49. The -335 speed grade will operate with
including jitter, the DLL is required to be reset.
This is followed by 200 clock cycles (before READ
commands).
possible through the module pin, not what each
memory device contributes.
LOW, it is defined as a steady state logic HIGH or
LOW.
= 40ns and
frequency.
Micron Technology, Inc., reserves the right to change products or specifications without notice.
184-PIN DDR SDRAM RDIMM
t
RAS (MAX) = 120,000ns at any slower
©2004 Micron Technology, Inc. All rights reserved.
t
RAS (MIN)