mt18vdvf12872dg-40b Micron Semiconductor Products, mt18vdvf12872dg-40b Datasheet - Page 8

• Manufacturer Part Number: mt18vdvf12872dg-40b
• Description: 1gb X72, Ecc, Dr 184-pin Ddr Vlp Rdimm
• Manufacturer: Micron Semiconductor Products

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Table 8:
PDF: 09005aef81c73825/Source: 09005aef81c73837
DVF18C_128x72D.fm - Rev. B 10/07 EN
Parameter/Condition
Operating one bank active-precharge current:
DQ, DM, and DQS inputs changing once per clock cycle; Address and control inputs
changing once every two clock cycles
Operating one bank active-read-precharge current: BL = 2;
t
Precharge power-down standby current: All device banks idle; Power-down mode;
t
Idle standby current: CS# = HIGH; All device banks idle;
Address and other control inputs changing once per clock cycle; V
and DM
Active power-down standby current: One device bank active; Power-down mode;
t
Active standby current: CS# = HIGH; CKE = HIGH; One device bank; Active-
precharge;
per clock cycle; Address and other control inputs changing once per clock cycle
Operating burst read current: BL = 2; Continuous burst reads; One device bank
active; Address and control inputs changing once per clock cycle;
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Operating burst write current: BL = 2; Continuous burst writes; One device bank
active; Address and control inputs changing once per clock cycle;
DM, and DQS inputs changing twice per clock cycle
Auto refresh current
Self refresh current: CKE ≤ 0.2V
Operating bank interleave read current: Four device bank interleaving reads;
BL = 4 with auto precharge;
inputs change only during active READ or WRITE commands
DD
CK =
CK =
CK =
OUT
= 0mA
Specifications
t
t
t
CK (MIN); I
CK (MIN); CKE = LOW
CK (MIN); CKE = LOW
t
RC =
I
Values are shown for the MT46V64M8 DDR SDRAM only and are computed from values specified in the
512Mb (64 Meg x 8) component data sheet
DD
t
OUT
RAS (MAX);
Specifications and Conditions – 1GB
Notes:
= 0mA; Address and control inputs changing once per clock cycle
1. Value calculated as one module rank in this operating condition; all other module ranks are
2. Value calculated reflects all module ranks in this operating condition.
t
RC =
t
CK =
in I
t
DD
RC (MIN);
t
CK (MIN); DQ, DM, and DQS inputs changing twice
2P (CKE LOW) mode.
t
CK =
t
t
CK (MIN); Address and control
RC =
t
t
CK =
RC (MIN);
8
t
t
1GB (x72, ECC, DR) 184-Pin DDR VLP RDIMM
REFC =
REFC = 7.8125µs
t
CK (MIN); CKE = HIGH;
t
IN
RC =
t
t
CK =
CK =
= V
t
CK =
t
RFC (MIN)
REF
t
Micron Technology, Inc., reserves the right to change products or specifications without notice.
RC (MIN);
t
t
CK (MIN); DQ,
CK (MIN);
for DQ, DQS,
t
CK (MIN);
Symbol
I
I
I
I
I
I
I
DD
DD
DD
I
I
DD
I
I
I
Electrical Specifications
DD
DD
DD
DD
DD
DD
DD
DD
4W
3N
5A
2P
3P
4R
2F
0
1
5
6
7
1
1
2
2
1
2
2
2
1
2
2
1
©2005 Micron Technology, Inc. All rights reserved.
1,440
1,710
1,800
1,755
1,800
6,210
4,095
-40B
990
810
198
90
90
1,215
1,485
1,530
1,620
5,220
3,690
-335
810
630
900
180
90
90
Units
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA