mt18jsf25672az Micron Semiconductor Products, mt18jsf25672az Datasheet - Page 18

• Manufacturer Part Number: mt18jsf25672az
• Description: 2gb, 4gb X72, Ecc, Dr 240-pin Ddr3 Sdram Udimm
• Manufacturer: Micron Semiconductor Products

Table 19: Capability Register Bit Description (Continued)
Configuration Register
Table 20: Configuration Register (Address: 0x01)
Table 21: Configuration Register Bit Descriptions
PDF: 09005aef83606b46
jsf18c256_512x72az.pdf – Rev. B 5/09
Critical lock
Bit
RFU
0
1
2
3
15
bit
7
15:5
Bit
4:3
2
Description
Event mode
0: Comparator mode
1: Interrupt mode
EVENT# polarity
0: Active LOW
1: Active HIGH
Critical event only
0: EVENT# trips on alarm or critical temperature event
1: EVENT# trips only if critical temperature is reached
Event output control
0: Event output disabled
1: Event output enabled
Alarm lock bit
RFU
Description
Wider range
0: Temperatures lower than 0°C are clamped to a binary value of 0
1: Temperatures below 0°C can be read
Temperature resolution
00: 0.5°C LSB
01: 0.25°C LSB
10: 0.125°C LSB
11: 0.0625°C LSB
0: Must be set to zero
14
6
Clear event
RFU
13
5
Temperature Sensor with Serial Presence-Detect EEPROM
2GB, 4GB (x72, ECC, DR) 240-Pin DDR3 SDRAM UDIMM
Event output
status
RFU
12
4
Bit
Bit
18
Event output
control
RFU
11
3
Notes
Event mode cannot be changed if either of the lock
bits is set.
EVENT# polarity cannot be changed if either of the
lock bits is set.
Micron Technology, Inc. reserves the right to change products or specifications without notice.
Critical event
only
10
2
Hysteresis
Event polarity
© 2009 Micron Technology, Inc. All rights reserved.
9
1
Event mode
Shutdown
mode
8
0