mt9htf12872pkz Micron Semiconductor Products, mt9htf12872pkz Datasheet - Page 10

• Manufacturer Part Number: mt9htf12872pkz
• Description: Ddr2 Sdram Mini-rdimm
• Manufacturer: Micron Semiconductor Products

Table 9: I
Values shown for MT47H128M8 DDR2 SDRAM only and are computed from values specified in the 1Gb (128 Meg x 8) com-
ponent data sheet
PDF: 09005aef83f993e9
htf9c64_128x72pkz.pdf – Rev. A 04/10 EN
Parameter/Condition
Operating one bank active-precharge current:
t
bus inputs are switching; Data bus inputs are switching
Operating one bank active-read-precharge current: I
(I
CKE is HIGH, S# is HIGH between valid commands; Address bus inputs are switching;
Data pattern is same as I
Precharge power-down current: All device banks idle;
LOW; Other control and address bus inputs are stable; Data bus inputs are floating
Precharge quiet standby current: All device banks idle;
HIGH, S# is HIGH; Other control and address bus inputs are stable; Data bus inputs
are floating
Precharge standby current: All device banks idle;
is HIGH; Other control and address bus inputs are switching; Data bus inputs are
switching
Active power-down current: All device banks open;
(I
Data bus inputs are floating
Active standby current: All device banks open;
(I
and address bus inputs are switching; Data bus inputs are switching
Operating burst write current: All device banks open; Continuous burst writes;
BL = 4, CL = CL (I
CKE is HIGH, S# is HIGH between valid commands; Address bus inputs are switching;
Data bus inputs are switching
Operating burst read current: All device banks open; Continuous burst reads; I
= 0mA; BL = 4, CL = CL (I
(I
ing; Data bus inputs are switching
Burst refresh current:
val; CKE is HIGH, S# is HIGH between valid commands; Other control and address bus
inputs are switching; Data bus inputs are switching
Self refresh current: CK and CK# at 0V; CKE ≤ 0.2V; Other control and address bus
inputs are floating; Data bus inputs are floating
Operating bank interleave read current: All device banks interleaving reads;
I
t
commands; Address bus inputs are stable during deselects; Data bus inputs are switch-
ing
RAS =
OUT
RC (I
DD
DD
DD
DD
), AL = 0;
); CKE is LOW; Other control and address bus inputs are stable;
),
); CKE is HIGH, S# is HIGH between valid commands; Address bus inputs are switch-
= 0mA; BL = 4, CL = CL (I
DD
t
RP =
t
),
RAS MIN (I
t
RRD =
DD
t
RP (I
t
CK =
Specifications and Conditions – 1GB
DD
DD
t
RRD (I
DD
); CKE is HIGH, S# is HIGH between valid commands; Other control
), AL = 0;
t
CK (I
); CKE is HIGH, S# is HIGH between valid commands; Address
DD
t
DD
DD
DD4W
CK =
),
),
), AL = 0;
t
t
RCD =
t
DD
CK =
RC =
t
CK (I
), AL =
512MB, 1GB (x72, ECC, SR) 244-Pin DDR2 SDRAM Mini-RDIMM
t
t
CK (I
RC (I
t
DD
RCD (I
t
CK =
); REFRESH command at every
t
RCD (I
DD
DD
),
),
DD
t
CK (I
t
t
); CKE is HIGH, S# is HIGH between valid
RAS =
RAS =
DD
DD
) - 1 ×
),
t
CK =
t
t
t
RAS MIN (I
RAS MAX (I
t
CK =
RAS =
t
CK =
t
CK (I
t
CK =
t
CK (I
t
CK (I
t
OUT
CK =
t
t
DD
t
CK (I
RAS MAX (I
CK =
10
t
DD
);
CK
= 0mA; BL = 4, CL = CL
DD
DD
DD
t
),
t
DD
CK =
),
CK (I
),
t
),
t
CK (I
); CKE is HIGH, S#
RAS =
t
t
RCD =
RC =
t
RP =
t
RFC (I
DD
Fast PDN exit
MR[12] = 0
Slow PDN exit
MR[12] = 1
t
CK (I
DD
Micron Technology, Inc. reserves the right to change products or specifications without notice.
DD
); CKE is
t
t
); CKE is
t
RC (I
RAS MAX
),
RP (I
t
RCD (I
DD
DD
t
RP =
) inter-
),
DD
DD
t
RC =
),
);
DD
t
RP
OUT
);
Symbol
I
I
I
I
I
I
I
DD4W
I
I
DD2Q
DD2N
DD3N
I
I
I
DD2P
DD3P
DD4R
DD0
DD1
DD5
DD6
DD7
© 2010 Micron Technology, Inc. All rights reserved.
IDD Specifications
1440
1440
2115
3015
-80E
-800
810
990
450
450
360
540
63
90
63
1215
1215
1935
2520
-667
765
900
360
360
270
495
63
90
63
Units
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA