mt9htf12872py-53e Micron Semiconductor Products, mt9htf12872py-53e Datasheet - Page 11

• Manufacturer Part Number: mt9htf12872py-53e
• Description: 256mb, 512mb, 1gb X72, Ecc, Sr 240-pin Ddr2 Sdram Rdimm
• Manufacturer: Micron Semiconductor Products

Table 11:
PDF: 09005aef82250868/Source: 09005aef82250815
HTF9C32_64_128x72.fm - Rev. E 6/08 EN
Parameter/Condition
Operating one bank active-precharge current:
t
commands; Address bus inputs are switching; Data bus inputs are
switching
Operating one bank active-read-precharge current: I
BL = 4, CL = CL (I
t
between valid commands; Address bus inputs are switching; Data
pattern is same as I
Precharge power-down current: All device banks idle;
CKE is LOW; Other control and address bus inputs are stable; Data bus
inputs are floating
Precharge quiet standby current: All device banks idle;
t
inputs are stable; Data bus inputs are floating
Precharge standby current: All device banks idle;
is HIGH, S# is HIGH; Other control and address bus inputs are switching;
Data bus inputs are switching
Active power-down current: All device banks open;
t
bus inputs are stable; Data bus inputs are floating
Active standby current: All device banks open;
t
valid commands; Other control and address bus inputs are switching;
Data bus inputs are switching
Operating burst write current: All device banks open; Continuous
burst writes; BL = 4, CL = CL (I
t
valid commands; Address bus inputs are switching; Data bus inputs are
switching
Operating burst read current: All device banks open; Continuous
burst reads, I
t
valid commands; Address bus inputs are switching; Data bus inputs are
switching
Burst refresh current:
(I
control and address bus inputs are switching; Data bus inputs are
switching
Self refresh current: CK and CK# at 0V; CKE ≤ 0.2V; Other control and
address bus inputs are floating; Data bus inputs are floating
Operating bank interleave read current: All device banks
interleaving reads, I
AL =
t
valid commands; Address bus inputs are stable during deselects; Data
bus inputs are switching
RC (I
RAS =
CK =
CK =
RAS =
RAS =
RAS =
RRD =
DD
) interval; CKE is HIGH, S# is HIGH between valid commands; Other
DD
t
RCD (I
t
t
CK (I
CK (I
t
t
t
t
t
),
RAS MIN (I
RAS MAX (I
RAS MAX (I
RAS MAX (I
RRD (I
t
RAS =
DD
DD
DD
OUT
DDR2 I
Values shown for MT47H64M8 DDR2 SDRAM only and are computed from values specified in the
512Mb (64 Meg x 8) component data sheet
); CKE is HIGH, S# is HIGH; Other control and address bus
); CKE is LOW; Other control and address
DD
) - 1 ×
DD
),
t
= 0mA; BL = 4, CL = CL (I
RAS MIN (I
DD
t
), AL = 0;
DD
DD
DD
DD
RCD =
OUT
t
),
CK (I
4W
),
),
),
DD
t
= 0mA; BL = 4, CL = CL (I
RCD =
t
t
t
t
RP =
RP =
RP =
CK =
Specifications and Conditions – 512MB
t
DD
RCD (I
DD
t
);
CK =
t
t
t
DD
t
RP (I
RP (I
RP (I
t
t
); CKE is HIGH, S# is HIGH between valid
CK (I
RCD (I
CK =
), AL = 0;
256MB, 512MB, 1GB (x72, ECC, SR) 240-Pin DDR2 SDRAM RDIMM
DD
t
DD
DD
DD
CK (I
DD
); CKE is HIGH, S# is HIGH between
t
DD
); CKE is HIGH, S# is HIGH between
); CKE is HIGH, S# is HIGH between
); CKE is HIGH, S# is HIGH between
CK (I
); REFRESH command at every
); CKE is HIGH, S# is HIGH
DD
DD
t
DD
),
CK =
), AL = 0;
t
),
RC =
t
RC =
t
DD
CK (I
t
t
),
RC (I
CK =
t
t
CK =
t
RC (I
DD
CK =
t
CK =
DD
),
t
CK (I
t
t
DD
),
Fast PDN exit
MR[12] = 0
Slow PDN exit
MR[12] = 1
CK (I
OUT
CK =
t
CK (I
t
),
CK (I
11
DD
= 0mA;
DD
t
),
CK (I
DD
DD
),
); CKE
t
),
RC =
t
DD
RFC
Micron Technology, Inc., reserves the right to change products or specifications without notice.
);
Symbol
I
I
I
I
I
I
I
DD
DD
DD
DD
I
I
DD
DD
DD
I
I
I
DD
DD
DD
DD
DD
4W
2Q
2N
3N
2P
3P
4R
0
1
5
6
7
1,035
1,755
1,845
2,070
2,700
-80E
-800
900
450
495
360
108
630
63
63
Electrical Specifications
1,530
1,620
1,620
2,160
-667
810
945
405
450
315
108
585
63
63
©2003 Micron Technology, Inc. All rights reserved.
1,260
1,305
1,530
2,025
-53E
720
855
360
405
270
108
495
63
63
1,035
1,035
1,485
1,980
-40E
720
810
315
360
225
108
405
63
63
Units
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA