mt9htf12872rhz Micron Semiconductor Products, mt9htf12872rhz Datasheet - Page 10

• Manufacturer Part Number: mt9htf12872rhz
• Description: Ddr2 Sdram Sordimm
• Manufacturer: Micron Semiconductor Products

IDD Specifications
Table 8: DDR2 I
Values shown for MT47H128M8 DDR2 SDRAM only and are computed from values specified in the 1Gb (128 Meg x 8) com-
ponent data sheet
PDF: 09005aef83ebee86
htf9c128x72rhz – Rev. A 3/10 EN
Parameter
Operating one bank active-precharge current:
=
are switching; Data bus inputs are switching
Operating one bank active-read-precharge current: I
(I
CKE is HIGH, S# is HIGH between valid commands; Address bus inputs are switching;
Data pattern is same as I
Precharge power-down current: All device banks idle;
Other control and address bus inputs are stable; Data bus inputs are floating
Precharge quiet standby current: All device banks idle;
S# is HIGH; Other control and address bus inputs are stable; Data bus inputs are floating
Precharge standby current: All device banks idle;
HIGH; Other control and address bus inputs are switching; Data bus inputs are switching
Active power-down current: All device banks open;
(I
Data bus inputs are floating
Active standby current: All device banks open;
(I
and address bus inputs are switching; Data bus inputs are switching
Operating burst write current: All device banks open; Continuous burst writes; BL =
4, CL = CL (I
HIGH, S# is HIGH between valid commands; Address bus inputs are switching; Data bus
inputs are switching
Operating burst read current: All device banks open; Continuous burst read, I
0mA; BL = 4, CL = CL (I
(I
ing; Data bus inputs are switching
Burst refresh current:
CKE is HIGH, S# is HIGH between valid commands; Other control and address bus in-
puts are switching; Data bus inputs are switching
Self refresh current: CK and CK# at 0V; CKE ≤ 0.2V; Other control and address bus
inputs are floating; Data bus inputs are floating
Operating bank interleave read current: All device banks interleaving reads; I
0mA; BL = 4, CL = CL (I
t
Address bus inputs are stable during deselects; Data bus inputs are switching
RRD =
DD
DD
DD
DD
t
RAS MIN (I
), AL = 0;
); CKE is LOW; Other control and address bus inputs are stable;
),
); CKE is HIGH, S# is HIGH between valid commands; Address bus inputs are switch-
t
RP =
t
RRD (I
t
DD
RP (I
DD
t
CK =
), AL = 0;
DD
); CKE is HIGH, S# is HIGH between valid commands; Address bus inputs
DD
),
DD
t
); CKE is HIGH, S# is HIGH between valid commands; Other control
t
RCD =
CK (I
Specifications and Conditions – 1GB
DD
DD
t
CK =
t
DD
DD4W
), AL = 0;
CK =
), AL =
t
RCD (I
),
t
RC =
t
CK (I
t
CK (I
t
RCD (I
DD
t
t
DD
CK =
); CKE is HIGH, S# is HIGH between valid commands;
RC (I
DD
),
); REFRESH command at every
DD
t
RAS =
DD
t
CK (I
) - 1 ×
),
t
RAS =
DD
t
RAS MAX (I
t
),
CK (I
t
t
RAS =
CK =
t
t
RAS MIN (I
CK =
DD
t
CK =
);
1GB (x72, SR) 200-Pin DDR2 SDRAM SORDIMM
t
CK =
t
CK (I
t
t
t
RAS MAX (I
CK =
CK (I
t
DD
OUT
CK =
t
t
CK (I
CK =
10
),
t
DD
CK
= 0mA; BL = 4, CL = CL
DD
DD
t
t
RP =
CK (I
),
t
DD
),
CK (I
),
t
t
CK (I
); CKE is HIGH, S# is
RAS =
t
t
RCD =
RC =
t
DD
t
RP (I
RFC (I
DD
DD
Fast PDN exit
MR[12] = 0
Slow PDN exit
MR[12] = 1
DD
),
Micron Technology, Inc. reserves the right to change products or specifications without notice.
),
); CKE is LOW;
t
t
t
); CKE is HIGH,
RC =
RC (I
DD
RAS MAX
t
t
RP =
RCD (I
DD
); CKE is
) interval;
DD
t
RC (I
t
RP
),
DD
OUT
t
OUT
RAS
);
DD
=
),
=
Symbol
I
I
I
I
I
I
I
I
DD3PF
DD3PS
DD4W
I
I
DD2Q
DD2N
DD3N
I
I
I
DD2P
DD4R
DD0
DD1
DD5
DD6
DD7
© 2010 Micron Technology, Inc. All rights reserved.
IDD Specifications
-80E/
1440
1440
2115
3015
800
810
990
450
450
360
540
63
90
63
1215
1215
1935
2520
-667
765
900
360
360
270
495
63
90
63
Units
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA