m368l2923fln Samsung Semiconductor, Inc., m368l2923fln Datasheet - Page 4
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m368l2923fln
Manufacturer Part Number
m368l2923fln
Description
Ddr Sdram Unbuffered Module
Manufacturer
Samsung Semiconductor, Inc.
Datasheet
1.M368L2923FLN.pdf
(17 pages)
1.0 Ordering Information
Note:
1. “L” of Part number(11th digit) stands for Lead-Free, Halogen-Free, and RoHS compliant products.
2.0 Operating Frequencies
3.0 Feature
• V
• V
• Double-data-rate architecture; two data transfers per clock cycle
• Bidirectional data strobe [DQ] (x4,x8) & [L(U)DQS] (x16)
• Differential clock inputs(CK and CK)
• DLL aligns DQ and DQS transition with CK transition
• Programmable Read latency : DDR333(2.5 Clock), DDR400(3 Clock)
• Programmable Burst length (2, 4, 8)
• Programmable Burst type (sequential & interleave)
• Edge aligned data output, center aligned data input
• Auto & Self refresh, 7.8us refresh interval(8K/64ms refresh)
• Serial presence detect with EEPROM
• PCB : Height 1,250 (mil) & single (256, 512MB), double (1GB) sided
• SSTL_2 Interface
• 66pin TSOP II package
• All of products are Lead-Free, Halogen-Free, and RoHS compliant
512MB, 1GB Unbuffered DIMM
DD
DD
: 2.5V ± 0.2V, V
: 2.6V ± 0.1V, V
M368L6523FLS-CCC/B3
M368L2923FLN-CCC/B3
Speed @CL2.5
CL-tRCD-tRP
Speed @CL3
Part Number
184Pin Unbuffered DIMM based on 512Mb F-die (x8, x16)
DDQ
DDQ
: 2.5V ± 0.2V for DDR333
: 2.6V ± 0.1V for DDR400
Density
512MB
1GB
CC(DDR400@CL=3)
166MHz
200MHz
3-3-3
Organization
128M x 64
2 of 15
64M x 64
64Mx8 (K4H510838F) * 8EA
64Mx8 (K4H510838F) * 16EA
Component Composition
B3(DDR333@CL=2.5)
Rev. 1.01 August 2008
166MHz
2.5-3-3
-
DDR SDRAM
1,250mil
1,250mil
Height