m393t5160qza Samsung Semiconductor, Inc., m393t5160qza Datasheet - Page 29

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m393t5160qza

Manufacturer Part Number
m393t5160qza
Description
240pin Registered Module Based On 1gb Q-die 72-bit Ecc
Manufacturer
Samsung Semiconductor, Inc.
Datasheet
RDIMM
15.0 240 Pin DDR2 Registered DIMM Clock Topology
Note:
CK0
CK0
1. The clock delay from the input of the PLL clock to the input of any DDR2 SDRAM or register will be set to 0ns (nominal).
2. Input, output, and feedback clock lines are terminated from line to line as shown, and not from line to ground.
3. Only one PLL output is shown per output type. Any additional PLL outputs will be wired in a similar manner.
4. Termination resistors for the PLL feedback path clocks are located as close to the input pin of the PLL as possible.
120 ohms
C
120 ohms
IN
Feedback In
0ns (nominal)
Feedback Out
PLL
29 of 29
OUTN
OUT1
DDR2 SDRAM
DDR2 SDRAM
Reg.A
Reg.B
C
DDR2 SDRAM
Rev. 1.1 July 2008
120 ohms
120 ohms

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