m470l3324du0 Samsung Semiconductor, Inc., m470l3324du0 Datasheet - Page 4

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m470l3324du0

Manufacturer Part Number
m470l3324du0
Description
256mb, 512mb, 1gb Unbuffered Sodimm
Manufacturer
Samsung Semiconductor, Inc.
Datasheet
1.0 Ordering Information
2.0 Operating Frequencies
3.0 Feature
• VDD : 2.5V ± 0.2V, VDDQ : 2.5V ± 0.2V for DDR266, 333
• VDD : 2.6V ± 0.1V, VDDQ : 2.6V ± 0.1V for DDR400
• Double-data-rate architecture; two data transfers per clock cycle
• Bidirectional data strobe [DQ] (x4,x8) & [L(U)DQS] (x16)
• Differential clock inputs(CK and CK)
• DLL aligns DQ and DQS transition with CK transition
• Programmable Read latency : DDR266(2, 2.5 Clock), DDR333(2.5 Clock), DDR400(3 Clock)
• Programmable Burst length (2, 4, 8)
• Programmable Burst type (sequential & interleave)
• Edge aligned data output, center aligned data input
• Auto & Self refresh, 7.8us refresh interval(8K/64ms refresh)
• Serial presence detect with EEPROM
• PCB : Height - 256MB(non ECC/ECC SS, 1250mil), 512MB/1GB(non ECC DS, 1250mil, ECC DS, 1400mil)
• SSTL_2 Interface
• 66pin TSOP II & 54pin sTSOP II
256MB, 512MB, 1GB Unbuffered SODIMM
RoHS compliant
M470L3324DU0-C(L)CC/B3/A2/B0
M470L6524DU0-C(L)CC/B3/A2/B0
M470L2923DV0-C(L)CC/B3/A2/B0
Speed @CL2.5
CL-tRCD-tRP
Speed @CL2
Speed @CL3
Part Number
200Pin Unbuffered SODIMM based on 512Mb D-die (x8, x16)
CC(DDR400@CL=3)
Pb-Free
166MHz
200MHz
3-3-3
-
package
Density
256MB
512MB
1GB
B3(DDR333@CL=2.5)
Organization
133MHz
166MHz
2.5-3-3
128M x 64
32M x 64
64M x 64
-
A2(DDR266@CL=2)
32Mx16 (K4H511638D) * 4EA
32Mx16 (K4H511638D) * 8EA
64Mx8 (K4H510838D) * 16EA
Component Composition
133MHz
133MHz
2-3-3
-
Rev. 1.01 January 2008
B0(DDR266@CL=2.5)
DDR SDRAM
100MHz
133MHz
2.5-3-3
-
1,250mil
1,250mil
1,250mil
Height

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