hys64t128020hm-5-a Infineon Technologies Corporation, hys64t128020hm-5-a Datasheet - Page 7
![no-image](/images/no-image-200.jpg)
hys64t128020hm-5-a
Manufacturer Part Number
hys64t128020hm-5-a
Description
214-pin Micro-dimm-ddr2-sdram Modules
Manufacturer
Infineon Technologies Corporation
Datasheet
1.HYS64T128020HM-5-A.pdf
(37 pages)
2
2.1
The pin configuration of the DDR2 SDRAM Micro-DIMM is listed by function in
abbreviations used in columns Pin and Buffer Type are explained in
numbering is depicted in
Table 5
Pin or Ball
No.
Clock Signals
122
194
123
195
43
147
Control Signals
165
62
Data Sheet
Pin Configuration and Block Diagrams
Pin Configuration
Pin Configuration of MDIMM
Name
CK0
CK1
CK0
CK1
CKE0
CKE1
NC
S0
S1
NC
Figure
Pin
Type
I
I
I
I
I
I
NC
I
I
NC
1.
Buffer
Type
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
Function
Clock Signal CK 1:0, Complementary Clock Signal CK 1:0
Note: The system clock inputs. All address and command lines are
Clock Enables 1:0
Note: Activates the DDR2 SDRAM CK signal when HIGH and
1. 2-rank module
Not Connected
Note: 1-rank module
Chip Select Rank 1:0
Note: Enables the associated DDR2 SDRAM command decoder
2. 2-rank module
Not Connected
Note: 1-rank module
sampled on the cross point of the rising edge of CK and the
falling edge of CK. A Delay Locked Loop (DLL) circuit is
driven from the clock inputs and output timing for read
operations is synchronized to the input clock.
deactivates the CK signal when LOW. By deactivating the
clocks, CKE0 initiates the Power Down Mode or the Self
Refresh Mode.
when LOW and disables the command decoder when HIGH.
When the command decoder is disabled, new commands
are ignored but previous operations continue. Rank 0 is
selected by S0; Rank 1 is selected by S1. The input signals
also disable all outputs (except CKE and ODT) of the
register(d) on the DIMM when both inputs are high. When S
is HIGH, all register outputs (except CK, ODT and Chip
select) remain in the previous state.
7
Micro-DIMM DDR2 SDRAM Modules
Table 6
Pin Configuration and Block Diagrams
HYS64T128020HM–[3.7/5]–A
and
Table 7
Table 5
04132004-S0LP-CL4Q
respectively. The pin
Rev. 1.2, 2005-08
(214 pins). The