hys64d32300hu-6-c Qimonda, hys64d32300hu-6-c Datasheet - Page 17

• Manufacturer Part Number: hys64d32300hu-6-c
• Description: 184- Pin Unbuffered Ddr Sdram Modules
• Manufacturer: Qimonda

6) For each of the terms, if not already an integer, round to the next highest integer.
7)
8) Fast slew rate ≥ 1.0 V/ns , slow slew rate ≥ 0.5 V/ns and < 1 V/ns for command/address and CK & CK slew rate > 1.0 V/ns,
9) These parameters guarantee device timing, but they are not necessarily tested on each device.
10) A maximum of eight Autorefresh commands can be posted to any given DDR SDRAM device.
11) The specific requirement is that DQS be valid (HIGH, LOW, or some point on a valid transition) on or before this CK edge.
12) The maximum limit for this parameter is not a device limit. The device operates with a greater value for this parameter, but
Internet Data Sheet
cycle time.
t
to a specific voltage level, but specify when the device is no longer driving (HZ), or begins driving (LZ).
measured between
A valid transition is defined as monotonic and meeting the input slew rate specifications of the device. When no writes were
previously in progress on the bus, DQS will be transitioning from Hi-Z to logic LOW. If a previous write was in progress,
DQS could be HIGH, LOW, or transitioning from HIGH to LOW at this time, depending on
system performance (bus turnaround) degrades accordingly.
HZ
and
t
LZ
transitions occur in the same access time windows as valid data transitions. These parameters are not referred
V
IH
(ac) and
V
IL
(ac).
HYS[64/72]D[16/32/64][300/301/320][G/H]U–[5/6]–C
17
Unbuffered DDR SDRAM Modules
t
CK
is equal to the actual system clock
t
DQSS
Electrical Characteristics
.
09152006-1LHY-N6G4
Rev. 1.11, 2007 - 01