hys64d16020gd Infineon Technologies Corporation, hys64d16020gd Datasheet - Page 10
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hys64d16020gd
Manufacturer Part Number
hys64d16020gd
Description
Unbuffered Ddr Sdram So Modules
Manufacturer
Infineon Technologies Corporation
Datasheet
1.HYS64D16020GD.pdf
(22 pages)
Table 4
Frontside
PIN#
40
41
42
43
44
45
46
47
Note: Pins 44, 45, 47, 49, 51, 134, 135, 140 and 144 are NC (“not connected”) on × 64 organised non-ECC
Table 5
128 MB
Note: Pins 71, 72, 73, 74, 77, 78, 79, 80, 83, 84, 89 and 91 are reserved for x72 variants of this module and are
Figure 1
Data Sheet
Density Organization Memory
modules.
not used on the x64 versions. Pin 86 is reserved for a registered variant of this module and is not used on
the unbuffered version
Symbol
DQ27
A2
V
A1
NC / CB0
NC / CB1
V
NC / DQS8
SS
DD
16M × 64
Pin Configuration (cont’d)
Address Format
Pin Configuration
Ranks
2
PIN#
85
86
87
88
89
90
91
92
SDRAMs # of
8M × 16
Symbol
V
DQS7
DQ58
DQ59
V
NC
SDA
SCL
DD
SS
SDRAMs
8
10
Backside
PIN#
132
133
134
135
136
137
138
139
SDRAM
density
128Mbit 12/2/9
Unbuffered DDR SDRAM SO Modules
Symbol
V
DQ31
NC / CB4
NC / CB5
V
CK0
V
CK0
SS
DDQ
SS
# of
row/rank/
columns
bits
HYS64D16020GD(L)-[7/8]-A
Refresh Period Interval
4K
PIN#
177
178
179
180
181
182
183
184
11042003-YIV7-VK6M
Rev. 1.02, 2004-01
Pin Configuration
64 ms
Symbol
DM7/DQS16
DQ62
DQ63
V
SA0
SA1
SA2
V
DDQ
DDSPD
15.6 µs