m391t5263az3 Samsung Semiconductor, Inc., m391t5263az3 Datasheet
m391t5263az3
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m391t5263az3 Summary of contents
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... UDIMM DDR2 Unbuffered SDRAM MODULE 240pin Unbuffered Module based on 2Gb A-die 68FBGA with Lead-Free and Halogen-Free INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS, AND IS SUBJECT TO CHANGE WITHOUT NOTICE. NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHER- WISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOL- OGY. ALL INFORMATION IN THIS DOCUMENT IS PROVIDED ON AS " ...
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... Input AC Logic Level 10.5 AC Input Test Conditions 11.0 IDD Specification Parameters Definition ................................................................................12 12.0 Operating Current Table : ........................................................................................................13 12.1 M378T5263AZ(H)3 : 4GB(256Mx8 *16) Module 12.2 M391T5263AZ(H)3 : 4GB(256Mx8 *18) ECC Module 13.0 Input/Output Capacitance ........................................................................................................14 14.0 Electrical Characteristics & AC Timing for DDR2-800/667/533 .............................................14 14.1 Refresh Parameters by Device Density 14.2 Speed Bins and CL, tRCD, tRP, tRC and tRAS for Corresponding Bin 14 ...
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UDIMM Revision History Revision Month Year 1.0 December 2007 1.1 July 2008 - Initial Release - Applied JEDEC update(JESD79-2E timing table DDR2 SDRAM History Rev. 1.1 July 2008 ...
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... Package: 68ball FBGA - 128Mx8 • All of base components are Lead-Free, Halogen-Free, and RoHS compliant Note: For detailed DDR2 SDRAM operation, please refer to Samsung’s Device operation & Timing diagram. 3.0 Address Configuration Organization 256Mx8(2Gb) based Module Density Organization Component Composition x64 Non ECC ...
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... 149 DQ22 DQ18 150 DQ23 Connect, RFU = Reserved for Future Use 1. The TEST pin is reserved for bus analysis tools and is not connected on standard memory module products (DIMMs.) Front Pin Back Pin Front V DQ19 151 152 ...
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... SS 30 DQ18 150 DQ23 Connect, RFU = Reserved for Future Use 1. The TEST pin is reserved for bus analysis tools and is not connected on standard memory module products (DIMMs.) 6.0 Pin Description Pin Name Description A0-A14 DDR2 SDRAM address bus BA0-BA2 DDR2 SDRAM bank select ...
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... DM loading matches the DQ and DQS loading. Power and ground for DDR2 SDRAM input buffers, and core logic planes on these modules. DDQ Data strobe for input and output data. For Rawcards using x16 orginized DRAMs DQ0-7 connect to the LDQS pin of the DRAMs and DQ8-17 connect to the UDQS pin of the DRAM These signals and tied at the system planar to either V address range ...
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... UDIMM 8.0 Functional Block Diagram : 8.1 4GB, 512Mx64 Module - M378T5263AZ(H)3 (Populated as 2 rank of x8 DDR2 SDRAMs DQS0 DQS0 DM0 DM CS DQS DQS DQ0 I/O 0 DQ1 I DQ2 I/O 2 DQ3 I/O 3 DQ4 I/O 4 DQ5 I/O 5 DQ6 I/O 6 DQ7 I/O 7 DQS1 DQS1 DM1 DM CS DQS DQS DQ8 I/O 0 DQ9 I DQ10 I/O 2 DQ11 ...
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... UDIMM 8.2 4GB, 512Mx72 ECC Module - M391T5263AZ(H DQS0 DQS0 DM0 DM CS DQS DQS DQ0 I/O 0 DQ1 I DQ2 I/O 2 DQ3 I/O 3 DQ4 I/O 4 DQ5 I/O 5 DQ6 I/O 6 DQ7 I/O 7 DQS1 DQS1 DM1 DM CS DQS DQS DQ8 I/O 0 DQ9 I DQ10 I/O 2 DQ11 I/O 3 DQ12 I/O 4 DQ13 I/O 5 DQ14 I/O 6 DQ15 I/O 7 DQS2 DQS2 DM2 DM CS DQS DQS ...
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UDIMM 9.0 Absolute Maximum DC Ratings Symbol Parameter V Voltage on V pin relative Voltage on V pin relative to V DDQ DDQ V Voltage on V pin relative to V DDL DDL V V ...
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UDIMM 10.2 Operating Temperature Condition Symbol T Operating Temperature OPER Note : 1. Operating Temperature is the case surface temperature on the center/top side of the DRAM. For the measurement conditions, please refer to JESD51.2 standard ...
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UDIMM 11.0 IDD Specification Parameters Definition (IDD values are for full operating range of Voltage and Temperature) Symbol Operating one bank active-precharge current; IDD0 tCK = tCK(IDD), tRC = tRC(IDD), tRAS = tRASmin(IDD); CKE is HIGH HIGH between ...
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... IDD3N 1,260 IDD4W 2,070 IDD4R 2,340 IDD5 3,060 IDD6 270 IDD7 3,690 * Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading cap. 800@CL6 667@CL=5 CF7 CE6 1,240 1,160 1,440 1,320 240 240 880 800 ...
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UDIMM 13.0 Input/Output Capacitance Parameter Non-ECC Input capacitance, CK and CK Input capacitance, CKE and CS Input capacitance, Addr, RAS, CAS, WE Input/output capacitance, DQ, DM, DQS, DQS ECC Input capacitance, CK and CK Input capacitance, CKE and CS Input ...
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UDIMM 14.3 Timing parameters by speed grade (DDR2-800 and DDR2-667) (Refer to notes for informations related to this table at the component datasheet) Parameter DQ output access time from CK/CK DQS output access time from CK/CK Average clock HIGH pulse ...
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UDIMM Parameter Four Activate Window for 1KB page size products Four Activate Window for 2KB page size products CAS to CAS command delay Write recovery time Auto precharge write recovery + precharge time Internal write to read command delay Internal ...
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UDIMM 14.4 Timing parameters by speed grade (DDR2-533) (Refer to notes for informations related to this table at the component datasheet) Parameter DQ output access time from CK/CK DQS output access time from CK/CK CK HIGH pulse width CK LOW ...
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UDIMM Parameter Four Activate Window for 1KB page size products Four Activate Window for 2KB page size products CAS to CAS command delay Write recovery time Auto precharge write recovery + precharge time Internal write to read command delay Internal ...
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... UDIMM 15.0 Physical Dimensions : 256Mbx8 based 512Mx64(x72) Module(2 Rank) (2) 2.50 63.00 5.00 4.00 2.50 1.50±0.10 Detail A The used device is 256M x8 DDR2 SDRAM, FBGA. DDR2 SDRAM Part NO : K4T2G084QA - M378(91)T5263AZ(H)3 133.35 131.35 128.95 N/A (for x64) ECC SPD (for x72 55.00 N/A (for x64) ECC (for x72) 4.00 0.80±0.05 3.80 1.00 Detail ...