mt9v011ia9stces aptina, mt9v011ia9stces Datasheet - Page 10

• Manufacturer Part Number: mt9v011ia9stces
• Description: Mt9v011 1/4-inch Vga Digital Image Sensor
• Manufacturer: aptina

Output Data Timing
Figure 7:
Figure 8:
PDF:0560901182/Source 6061803135
MT9V011_IBGA_DS - Rev. C 6/10 EN
Timing Example of Pixel Data
Row Timing and FRAME_VALID/LINE_VALID Signals
D
OUT9
LINE_VALID
-D
Number of master clocks
PIXCLK
OUT0
FRAME_VALID
The data output of the MT9V011 is synchronized with the PIXCLK output. When
LINE_VALID is HIGH, one 10-bit pixel datum is output every PIXCLK period.
The rising edges of the PIXCLK signal are nominally timed to occur one-half of a master
clock period after the D
data. The PIXCLK is HIGH for one complete master clock period and then LOW for one
complete master clock period. It is continuously enabled, even during the blanking
period. The MT9V011 can be programmed to move the PIXCLK edge relative to the D
transitions from +1 to -1 master clock, in steps of one-half of a master clock. This can be
achieved by programming the corresponding bits in Reg0x07.
The parameters P, A, and Q in Figure 8 are defined in Table 3.
LINE_VALID
Blanking
(9:0)
P 0
P
(9:0)
OUT
P 1
A
edges. This allows PIXCLK to be used as a clock to latch the
10
(9:0)
Valid Image Data
P2
Q
(9:0)
MT9V011 1/4-INCH VGA DIGITAL IMAGE SENSOR
P 3
. . .
. . .
. . .
(9:0)
P 4
A
. . . .
. . . .
. . . .
. . . .
P n-1
(9:0)
Q
Aptina reserves the right to change products or specifications without notice.
(9:0)
P n
A
Blanking
P
©2009 Aptina Imaging Corporation. All rights reserved.
Preliminary
OUT