w332m64v-xbx White Electronic Designs Corporation, w332m64v-xbx Datasheet - Page 8

• Manufacturer Part Number: w332m64v-xbx
• Description: 32mx64 Synchronous Dram
• Manufacturer: White Electronic Designs Corporation

two clocks earlier. If a given DQM signal was registered
HIGH, the cor re spond ing I/Os will be High-Z two clocks
later; if the DQM signal was registered LOW, the I/Os will
provide valid data.
WRITE
The WRITE command is used to initiate a burst write
access to an active row. The value on the BA0, BA1 inputs
selects the bank, and the address provided on inputs A0-9
se lects the starting column location. The value on input A10
de ter mines whether or not AUTO PRECHARGE is used. If
AUTO PRECHARGE is selected, the row being accessed
will be precharged at the end of the WRITE burst; if AUTO
PRECHARGE is not selected, the row will remain open for
sub se quent accesses. Input data appearing on the I/Os
is written to the memory array subject to the DQM input
logic level ap pear ing co in ci dent with the data. If a given
DQM signal is registered LOW, the cor re spond ing data
will be written to memory; if the DQM signal is registered
HIGH, the cor re spond ing data inputs will be ignored, and a
WRITE will not be executed to that byte/column location.
PRECHARGE
The PRECHARGE command is used to deactivate the
open row in a particular bank or the open row in all banks.
The bank(s) will be available for a subsequent row access
a specifi ed time (tRP) after the PRECHARGE command
is is sued. Input A10 determines wheth er one or all banks
are to be precharged, and in the case where only one
bank is to be precharged, inputs BA0, BA1 select the bank.
Oth er wise BA0, BA1 are treated as “Don’t Care.” Once a
bank has been precharged, it is in the idle state and must
be activated pri or to any READ or WRITE commands being
is sued to that bank.
AUTO PRECHARGE
AUTO PRECHARGE is a feature which performs the same
in di vid u al-bank PRECHARGE function de scribed above,
with out re quir ing an explicit command. This is ac com plished
by using A10 to enable AUTO PRECHARGE in conjunction
with a spe cifi c READ or WRITE command. A precharge of
the bank/row that is ad dressed with the READ or WRITE
com mand is au to mat i cal ly performed upon com ple tion of
the READ or WRITE burst, except in the full-page burst
mode, where AUTO PRECHARGE does not ap ply. AUTO
PRECHARGE is non per sis tent in that it is either enabled or
disabled for each in di vid u al READ or WRITE com mand.
AUTO PRECHARGE ensures that the precharge is initiated
at the earliest valid stage within a burst. The user must not
February 2005
Rev. 0
White Electronic Designs
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is sue another command to the same bank until the precharge
time (t
PRECHARGE com mand was issued at the earliest possible
time.
BURST TERMINATE
The BURST TERMINATE command is used to truncate
either fi xed-length or full-page bursts. The most recently
reg is tered READ or WRITE command prior to the BURST
TER MI NATE command will be truncated.
AUTO REFRESH
AUTO REFRESH is used during normal op er a tion of
the SDRAM and is analagous to CAS#-BEFORE-RAS#
(CBR) RE FRESH in con ven tion al DRAMs. This com mand
is nonpersistent, so it must be issued each time a refresh
is required.
The addressing is generated by the internal refresh
con trol ler. This makes the address bits “Don’t Care”
during an AUTO RE FRESH command. Each 512Mb
SDRAM requires 8,192 AUTO RE FRESH cycles every
refresh period (t
RE FRESH command will meet the refresh re quire ment
and ensure that each row is re freshed. Al ter na tive ly, 8,192
AUTO RE FRESH com mands can be is sued in a burst at
the minimum cycle rate (t
(t
SELF REFRESH*
The SELF REFRESH command can be used to retain data
in the SDRAM, even if the rest of the system is powered
down. When in the self refresh mode, the SDRAM retains
data with out external clocking. The SELF RE FRESH
command is ini ti at ed like an AUTO REFRESH com mand
except CKE is dis abled (LOW). Once the SELF RE FRESH
command is reg is tered, all the inputs to the SDRAM
become “Don’t Care,” with the exception of CKE, which
must remain LOW.
Once self refresh mode is engaged, the SDRAM provides
its own internal clocking, causing it to perform its own
AUTO REFRESH cycles. The SDRAM must remain in
self refresh mode for a minimum period equal to tRAS and
may remain in self refresh mode for an indefi nite period
beyond that.
The procedure for exiting self refresh requires a sequence
of commands. First, CLK must be stable (stable clock is
defined as a signal cycling within timing con straints
* Self refresh available in commercial and industrial tem per a tures only.
REF
).
RP
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) is completed. This is determined as if an explicit
REF
). Pro vid ing a dis trib ut ed AUTO
RC
W332M64V-XBX
), once every refresh period