w332m64v-xsbx White Electronic Designs Corporation, w332m64v-xsbx Datasheet - Page 12

• Manufacturer Part Number: w332m64v-xsbx
• Description: 32mx64 Synchronous Dram
• Manufacturer: White Electronic Designs Corporation

NOTES:
1. All voltages referenced to V
2. This parameter is not tested but guaranteed by design. f = 1 MHz, T
3. I
4. Enables on-chip refresh and address counters.
5. The minimum specifi cations are used only to indicate cycle time at which proper
6. An initial pause of 100µs is required after power-up, followed by two AUTO
7. AC characteristics assume t
8. In addition to meeting the transition rate specifi cation, the clock and CKE must
9. Outputs measured at 1.5V with equivalent load:
10. t
11. AC timing and I
12. Other input signals are allowed to transition no more than once every two clocks
13. I
September 2005
Rev. 3
Parameter/Condition
READ/WRITE command to READ/WRITE command (17)
CKE to clock disable or power-down entry mode (14)
CKE to clock enable or power-down exit setup mode (14)
DQM to input data delay (17)
DQM to data mask during WRITEs
DQM to data high-impedance during READs
WRITE command to input data delay (17)
Data-in to ACTIVE command (15)
Data-in to PRECHARGE command (16)
Last data-in to burst STOP command (17)
Last data-in to new READ/WRITE command (17)
Last data-in to PRECHARGE command (16)
LOAD MODE REGISTER command to ACTIVE or REFRESH command (25)
Data-out to high-impedance from PRECHARGE command (17)
with minimum cycle time and the outputs open.
operation over the full temperature range is ensured.
REFRESH commands, before proper device operation is ensured. (V
must be powered up simultaneously.) The two AUTO REFRESH command wake-
ups should be repeated any time the t
transit between V
a reference to V
High-Z.
crossover point.
and are otherwise at valid V
CC
HZ
CC
defi nes the time at which the output achieves the open circuit condition; it is not
is dependent on output loading and cycle rates. Specifi ed values are obtained
spec i fi ca tions are tested after the device is properly initialized.
CC
OH
IH
tests have V
or V
and V
White Electronic Designs
Q
OL
. The last valid data element will meet t
IL
(or between V
SS
IH
T
= 1ns.
.
or V
IL
AC FUNCTIONAL CHARACTERISTICS (NOTES 5,6,7,8,9,11)
= 0V and V
IL
levels.
REF
IL
refresh re quire ment is exceeded.
and V
IH
= 3V, with timing referenced to 1.5V
50pF
IH
) in a monotonic manner.
OH
before going
A
= 25°C.
CC
and V
CCQ
CL = 3
CL = 2
12
14. Timing actually specifi ed by t
15. Timing actually specifi ed by t
16. Timing actually specifi ed by t
17. Required clocks are specifi ed by JEDEC functionality and are not de pen dent on
18. The I
19. Address transitions average one transition every two clocks.
20. CLK must be toggled a minimum of two times during this period.
21. V
22. The clock frequency must remain constant (stable clock is defi ned as a signal
23. Auto precharge mode only. The precharge timing budget (t
24. Precharge mode only.
25. JEDEC and PC100 specify three clocks.
26. Parameter guaranteed by design.
27. Self refresh available in commercial and industrial temperatures only.
cycle rate.
minimum cycle rate.
any timing parameter.
that the maximum cycle rate is slower as the CAS latency is reduced.
cannot be greater than one third of the cycle rate. V
for a pulse width 3ns.
cycling within timing constraints specifi ed for the clock pin) during access or
precharge states (READ, WRITE, including t
CKE may be used to reduce the data rate.
after the fi rst clock delay, after the last WRITE is executed.
IH
overshoot: V
Symbol
CC
t
t
t
t
t
t
t
t
CKED
t
t
t
t
t
t
t
DQM
DWD
CCD
PED
DQD
DQZ
MRD
ROH
ROH
DAL
DPL
BDL
CDL
RDL
current will decrease as the CAS latency is reduced. This is due to the fact
White Electronic Designs Corporation • [phone] • www.wedc.com
IH
(MAX) = V
-100
1
1
1
0
0
2
0
4
2
1
1
2
2
3
2
CKS
WR
WR
CCQ
.
; clock(s) specifi ed as a reference only at minimum
plus t
+ 2V for a pulse width 3ns, and the pulse width
W332M64V-XSBX
RP
; clock(s) specifi ed as a reference only at
-125
—
1
1
1
0
0
2
0
5
2
1
1
2
2
3
WR
, and PRECHARGE com mands).
IL
undershoot: V
-133
—
1
1
1
0
0
2
0
5
2
1
1
2
2
3
RP
) begins 7.5ns/7ns
IL
(MIN) = -2V
Units
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
CK
CK
CK
CK
CK
CK
CK
CK
CK
CK
CK
CK
CK
CK
CK