gs8662d08bgd-400i GSI Technology, gs8662d08bgd-400i Datasheet - Page 8

• Manufacturer Part Number: gs8662d08bgd-400i
• Description: 72mb Sigmaquad-ii Tm Burst Of 4 Sram
• Manufacturer: GSI Technology

SigmaQuad-II B4 SRAM DDR Write
The status of the Address Input, W, and R pins are sampled by the rising edges of K. W and R high causes chip disable. A low on
the Write Enable-bar pin, W, and a high on the Read Enable-bar pin, R, begins a write cycle. W is always ignored if the previous
command was a write command. Data is clocked in by the next rising edge of K, the rising edge of K after that, the next rising edge
of K, and finally by the next rising edge of K.
Special Functions
Byte Write and Nybble Write Control
Byte Write Enable pins are sampled at the same time that Data In is sampled. A high on the Byte Write Enable pin associated with
a particular byte (e.g., BW0 controls D0–D8 inputs) will inhibit the storage of that particular byte, leaving whatever data may be
stored at the current address at that byte location undisturbed. Any or all of the Byte Write Enable pins may be driven high or low
during the data in sample times in a write sequence.
Each write enable command and write address loaded into the RAM provides the base address for a 4 beat data transfer. The x18
version of the RAM, for example, may write 72 bits in association with each address loaded. Any 9-bit byte may be masked in any
write sequence.
Nybble Write (4-bit) control is implemented on the 8-bit-wide version of the device. For the x8 version of the device, “Nybble
Write Enable” and “NBx” may be substituted in all the discussion above.
Rev: 1.02a 5/2011
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Address
BWx
CQ
CQ
W
R
D
C
C
Q
K
K
A
Write A
A
NOP
B
Read B
8/34
A+3
C
Write C
GS8662D08/09/18/36BD-400/350/333/300/250
B
D
C
Read D
B+1
B+2
E
Write E
B+3
D
© 2011, GSI Technology
NOP
D+1
D+2