gs8321e36agd-333v GSI Technology, gs8321e36agd-333v Datasheet

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gs8321e36agd-333v

Manufacturer Part Number
gs8321e36agd-333v
Description
2m X 18, 1m X 32, 1m X 36 36mb Sync Burst Srams
Manufacturer
GSI Technology
Datasheet
165-Bump BGA
Commercial Temp
Industrial Temp
Features
• FT pin for user-configurable flow through or pipeline operation
• Dual Cycle Deselect (DCD) operation
• IEEE 1149.1 JTAG-compatible Boundary Scan
• 1.8 V or 2.5 V core power supply
• 1.8 V or 2.5 V I/O supply
• LBO pin for Linear or Interleaved Burst mode
• Internal input resistors on mode pins allow floating mode pins
• Default to Interleaved Pipeline mode
• Byte Write (BW) and/or Global Write (GW) operation
• Internal self-timed write cycle
• Automatic power-down for portable applications
• JEDEC-standard 165-bump BGA package
• RoHS-compliant 165-bump BGA package available
Functional Description
Applications
The GS8321E18/32/36AD-xxxV is a 37,748,736-bit high
performance synchronous SRAM with a 2-bit burst address
counter. Although of a type originally developed for Level 2
Cache applications supporting high performance CPUs, the
device now finds application in synchronous SRAM
applications, ranging from DSP main store to networking chip
set support.
Controls
Addresses, data I/Os, chip enable (E1), address burst control
inputs (ADSP, ADSC, ADV) and write control inputs (Bx, BW,
GW) are synchronous and are controlled by a positive-edge-
triggered clock input (CK3). Output enable (G) and power down
control (ZZ) are asynchronous inputs. Burst cycles can be
initiated with either ADSP or ADSC inputs. In Burst mode,
subsequent burst addresses are generated internally and are
controlled by ADV. The burst address counter may be
configured to count in either linear or interleave order with the
Rev: 1.00a 2/2011
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Through
Pipeline
3-1-1-1
2-1-1-1
Flow
Curr
Curr
Curr
Curr
tCycle
tCycle
2M x 18, 1M x 32, 1M x 36
36Mb Sync Burst SRAMs
t
t
(x32/x36)
(x32/x36)
KQ
KQ
(x18)
(x18)
Parameter Synopsis
1/30
-333
290
335
210
240
3.0
3.0
5.0
5.0
Linear Burst Order (LBO) input. The Burst function need not be
used. New addresses can be loaded on every cycle with no
degradation of chip performance.
Flow Through/Pipeline Reads
The function of the Data Output register can be controlled by the
user via the FT mode pin (Pin 14). Holding the FT mode pin low
places the RAM in Flow Through mode, causing output data to
bypass the Data Output Register. Holding FT high places the
RAM in Pipeline mode, activating the rising-edge-triggered Data
Output Register.
DCD Pipelined Reads
The GS8321E18/32/36AD-xxxV is a DCD (Dual Cycle
Deselect) pipelined synchronous SRAM. SCD (Single Cycle
Deselect) versions are also available. DCD SRAMs pipeline
disable commands to the same degree as read commands. DCD
RAMs hold the deselect command for one full cycle and then
begin turning off their outputs just after the second rising edge of
clock.
Byte Write and Global Write
Byte write operation is performed by using Byte Write enable
(BW) input combined with one or more individual byte write
signals (Bx). In addition, Global Write (GW) is available for
writing all bytes at one time, regardless of the Byte Write control
inputs.
Sleep Mode
Low power (Sleep mode) is attained through the assertion (High)
of the ZZ signal, or by stopping the clock (CK). Memory data is
retained during Sleep mode.
Core and Interface Voltages
The GS8321E18/32/36AD-xxxV operates on a 1.8 V or 2.5 V
power supply. All inputs are 1.8 V or 2.5 V compatible. Separate
output power (V
from the internal circuits and are 1.8 V or 2.5 Vcompatible.
-250
230
270
180
210
3.0
4.0
5.5
5.5
-200
190
225
160
185
3.0
5.0
6.5
6.5
DDQ
) pins are used to decouple output noise
-150
155
180
140
160
3.8
6.7
7.5
7.5
GS8321E18/32/36AD-xxxV
Unit
mA
mA
mA
mA
ns
ns
ns
ns
© 2011, GSI Technology
333 MHz–150 MHz
1.8 V or 2.5 V V
1.8 V or 2.5 V I/O
Preliminary
DD

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gs8321e36agd-333v Summary of contents

Page 1

... Curr 240 210 (x32/x36) 1/30 Preliminary GS8321E18/32/36AD-xxxV 333 MHz–150 MHz 2.5 V I/O ) pins are used to decouple output noise DDQ -200 -150 Unit 3.0 3.8 ns 5.0 6.7 ns 190 155 mA 225 180 mA 6.5 7.5 ns 6.5 7.5 ns 160 140 mA 185 160 mA © 2011, GSI Technology DD ...

Page 2

... DQPA C DDQ V NC DQA D DDQ V NC DQA E DDQ V NC DQA F DDQ V NC DQA G DDQ DQA NC J DDQ V DQA NC K DDQ V DQA NC L DDQ V DQA NC M DDQ DDQ © 2011, GSI Technology ...

Page 3

... DDQ V DQB DQB D DDQ V DQB DQB E DDQ V DQB DQB F DDQ V DQB DQB G DDQ DQA DQA J DDQ V DQA DQA K DDQ V DQA DQA L DDQ V DQA DQA M DDQ DDQ © 2011, GSI Technology ...

Page 4

... DQPB C DDQ V DQB DQB D DDQ V DQB DQB E DDQ V DQB DQB F DDQ V DQB DQB G DDQ DQA DQA J DDQ V DQA DQA K DDQ V DQA DQA L DDQ V DQA DQA M DDQ V NC DQPA N DDQ © 2011, GSI Technology ...

Page 5

... Linear Burst Order mode; active low Scan Test Mode Select Scan Test Data In Scan Test Data Out Scan Test Clock Must Connect Low Core power supply I/O and Core Ground Output driver power supply No Connect 5/30 Preliminary GS8321E18/32/36AD-xxxV I/Os; active low D © 2011, GSI Technology ...

Page 6

... Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS8321E18/32/36AD-xxxV Block Diagram Counter Load Register D Q Register D Q Register D Q Register D Q Register D Q Register D Q Register 6/30 Preliminary GS8321E18/32/36AD-xxxV A Memory Array – DQx1 DQx9 © 2011, GSI Technology ...

Page 7

... Note: The burst counter wraps to initial state on the 5th clock. 7/30 Preliminary GS8321E18/32/36AD-xxxV Function Linear Burst Interleaved Burst Flow Through Pipeline Active Standby A[1:0] A[1:0] A[1:0] A[1: © 2011, GSI Technology ...

Page 8

... may be used in any combination with BW to write single or multiple bytes. D 8/30 Preliminary GS8321E18/32/36AD-xxxV B B Notes and/ © 2011, GSI Technology ...

Page 9

... © 2011, GSI Technology 3 DQ High-Z High-Z High-Z High-Z High ...

Page 10

... Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Simplified State Diagram X Deselect First Write Burst Write CR CW 10/30 Preliminary GS8321E18/32/36AD-xxxV First Read Burst Read BW, and GW) control inputs, and © 2011, GSI Technology ...

Page 11

... Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Simplified State Diagram with G X Deselect First Write Burst Write 11/30 Preliminary GS8321E18/32/36AD-xxxV First Read Burst Read CR © 2011, GSI Technology ...

Page 12

... V +0.5 (≤ 4.6 V max.) DDQ –0 +0.5 (≤ 4.6 V max.) DD +/–20 +/–20 1.5 –55 to 125 –55 to 125 Min. Typ. Max. 1.7 1.8 2.0 2.3 2.5 2.7 V 1.7 1 2.3 2.5 DD Min. Typ. Max 0.3 — 0.3*V –0.3 — DD © 2011, GSI Technology Unit Unit Unit V V ...

Page 13

... I/O OUT 13/30 Preliminary GS8321E18/32/36AD-xxxV Typ. Max 100 θ JA (C°/W) θ JB (C°/W) Airflow = 2 m/s TBD TBD 20% tKC Typ. Max © 2011, GSI Technology Unit °C °C θ JC (C°/W) TBD Unit pF pF ...

Page 14

... GS8321E18/32/36AD-xxxV Figure 1 Output Load 1 * 50Ω 30pF V DDQ/2 * Distributed Test Jig Capacitance Min – ≥ –100 –1 uA OUT – 0.4 V DDQ DDQ = 2.375 V 1.7 V — — © 2011, GSI Technology Max 1 uA 100 — — 0.4 V 0.4 V ...

Page 15

... Rev: 1.00a 2/2011 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. 15/30 Preliminary GS8321E18/32/36AD-xxxV © 2011, GSI Technology ...

Page 16

... GSI Technology Unit ...

Page 17

... Deselect Deselect Write B Read C Read C+1 Read C+2 Read C+3 Cont tKL tKL tKH tKH tKC tKC ADSC initiated read and E3 only sampled with ADSC tS tKQ tOHZ tH tLZ Q(A) D(B) 17/30 Preliminary GS8321E18/32/36AD-xxxV Deselect Deselect Deselected with E1 tHZ Q(C) Q(C+1) Q(C+2) Q(C+3) © 2011, GSI Technology tKQX ...

Page 18

... Flow Through Mode Timing (DCD) Deselect Write B Read C Read C+1 Read C+2 Read C+3 Read C tKL tKL tKC tKC Fixed High tS tH ADSC initiated read masks ADSP E1 masks ADSP tH tS tOHZ tLZ Q(A) D(B) Q(C) 18/30 Preliminary GS8321E18/32/36AD-xxxV Deselect tH Deselected with E1 tKQX tHZ Q(C+1) Q(C+2) Q(C+3) Q(C) © 2011, GSI Technology ...

Page 19

... Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Sleep Mode Timing Diagram tKH tKH tKC tKC tKL tKL tZZS tZZH 19/30 Preliminary GS8321E18/32/36AD-xxxV 2. The duration of SB tZZR . The JTAG output DD . TDO should be left unconnected. SS © 2011, GSI Technology ...

Page 20

... Capture-DR state and then is placed between the TDI and TDO pins when the controller is moved to Shift-DR state. SAMPLE-Z, SAMPLE/PRELOAD and EXTEST instructions can be used to activate the Boundary Scan Register. Rev: 1.00a 2/2011 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Description 20/30 Preliminary GS8321E18/32/36AD-xxxV © 2011, GSI Technology ...

Page 21

... Control Signals Test Access Port (TAP) Controller Not Used 21/30 Preliminary GS8321E18/32/36AD-xxxV · · · TDO GSI Technology JEDEC Vendor ID Code © 2011, GSI Technology 0 1 ...

Page 22

... JTAG Tap Controller State Diagram 1 1 Select Capture DR 0 Shift Exit1 DR 0 Pause Exit2 Update 22/30 Preliminary GS8321E18/32/36AD-xxxV 1 Select Capture IR 0 Shift Exit1 IR 0 Pause Exit2 Update © 2011, GSI Technology ...

Page 23

... Z) and the Boundary Scan Register is connected between TDI and TDO when the TAP controller is moved to the Shift-DR state. RFU These instructions are Reserved for Future Use. In this device they replicate the BYPASS instruction. Rev: 1.00a 2/2011 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. 23/30 Preliminary GS8321E18/32/36AD-xxxV © 2011, GSI Technology ...

Page 24

... Instruction codes expressed in binary, MSB on left, LSB on right. 2. Default instruction automatically loaded at power-up and in test-logic-reset state. Rev: 1.00a 2/2011 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Description 24/30 Preliminary GS8321E18/32/36AD-xxxV Notes © 2011, GSI Technology ...

Page 25

... V 0.4 V — – 100 mV V — DDQ — 100 mV V JTAG Port AC Test Load DQ 50Ω 30pF V /2 DDQ * Distributed Test Jig Capacitance © 2011, GSI Technology ...

Page 26

... Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. JTAG Port Timing Diagram tTKC tTKC tTKH tTKH tTH tTS tTH tTS tTKQ tTH tTS Min Max Unit — — — — — ns — 26/30 Preliminary GS8321E18/32/36AD-xxxV tTKL tTKL © 2011, GSI Technology ...

Page 27

... Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. BOTTOM VIEW Ø0. Ø0. Ø0.40~0.60 (165x 1.0 10.0 13±0.05 B 0.20(4x) 27/30 Preliminary GS8321E18/32/36AD-xxxV A1 CORNER 1.0 © 2011, GSI Technology ...

Page 28

... GSI offers other versions this type of device in many different configurations and with a variety of different features, only some of which are covered in this data sheet. See the GSI Technology web site (www.gsitechnology.com) for a complete listing of current offerings. Rev: 1.00a 2/2011 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. ...

Page 29

... Ordering Information for GSI Synchronous Burst RAMs 1 Org Part Number GS8321E32AGD-200V GS8321E32AGD-150V GS8321E36AGD-333V GS8321E36AGD-250V GS8321E36AGD-200V GS8321E36AGD-150V GS8321E18AGD-333IV GS8321E18AGD-250IV GS8321E18AGD-200IV GS8321E18AGD-150IV GS8321E32AGD-333IV GS8321E32AGD-250IV GS8321E32AGD-200IV GS8321E32AGD-150IV GS8321E36AGD-333IV ...

Page 30

... Sync SRAM Datasheet Revision History Types of Changes File Name Format or Content 8321ExxA_V_r1 Rev: 1.00a 2/2011 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Page;Revisions;Reason • Creation of new datasheet 30/30 Preliminary GS8321E18/32/36AD-xxxV © 2011, GSI Technology ...

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