gs820e32a GSI Technology, gs820e32a Datasheet - Page 5

• Manufacturer Part Number: gs820e32a
• Description: 2mb Synchronous Burst Sram
• Manufacturer: GSI Technology

Mode Pin Functions
Note:
There are pull-up devices on the LBO and FT pins and a pull-down device on the ZZ pin, so those input pins can be unconnected and the chip will
operate in the default states as specified in the above table.
Burst Counter Sequences
Linear Burst Sequence
Note:
The burst counter wraps to initial state on the 5th clock.
Rev: 1.08 1/2009
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
1st address
2nd address
3rd address
4th address
Output Register Control
Power Down Control
Burst Order Control
Mode Name
A[1:0]
00
01
10
11
A[1:0]
01
10
00
11
A[1:0]
10
11
00
01
Pin Name
A[1:0]
LBO
00
01
10
ZZ
11
FT
5/20
H or NC
H or NC
L or NC
State
H
L
L
Interleaved Burst Sequence
Note:
The burst counter wraps to initial state on the 5th clock.
1st address
2nd address
3rd address
4th address
Standby, I
Interleaved Burst
Flow Through
Linear Burst
Function
Pipeline
A[1:0]
Active
00
01
10
11
DD
GS820E32AT-180/166/133/4/5
= I
A[1:0]
SB
01
00
11
10
A[1:0]
10
00
01
11
© 2000, GSI Technology
A[1:0]
11
10
01
00