psd934f2v-20mi STMicroelectronics, psd934f2v-20mi Datasheet - Page 10

• Manufacturer Part Number: psd934f2v-20mi
• Description: Flash In-system Programmable Isp Peripherals For 8-bit Mcus
• Manufacturer: STMicroelectronics

5.0
PSD9XX
Architectural
Overview
6
PSD9XX Family
PSD9XX devices contain several major functional blocks. Figure 1 shows the
architecture of the PSD9XX device family. The functions of each block are described
briefly in the following sections. Many of the blocks perform multiple functions and are
user configurable.
5.1 Memory
The PSD9XX contains the following memories:
Each of the memories is briefly discussed in the following paragraphs. A more detailed
discussion can be found in section 9.
The 1 or 2 Mbit Flash is the main memory of the PSD9XX. It is divided into eight
equally-sized sectors that are individually selectable.
The 256 Kbit secondary Flash memory is divided into four equally-sized sectors. Each
sector is individually selectable. This memory can hold boot code or data.
The SRAM is intended for use as a scratchpad memory or as an extension to the
microcontroller SRAM. If an external battery is connected to the PSD9XX’s Vstby pin, data
will be retained in the event of a power failure.
Each block of memory can be located in a different address space as defined by the user.
The access times for all memory types includes the address latching and DPLD decoding
time.
5.2 Page Register
The eight-bit Page Register expands the address range of the microcontroller by up to
256 times.The paged address can be used as part of the address space to access
external memory and peripherals or internal memory and I/O. The Page Register can also
be used to change the address mapping of blocks of Flash memory into different memory
spaces IAP.
5.3 PLDs
The device contains two combinatorial PLD blocks, each optimized for a different function,
as shown in Table 2. The functional partitioning of the PLDs reduces power consumption,
optimizes cost/performance, and eases design entry.
The Decode PLD (DPLD) is used to decode addresses and generate chip selects for the
PSD9XX internal memory and registers. The General Purpose PLD (GPLD) can
implement user-defined external chip selects and logic functions. The PLDs receive their
inputs from the PLD Input Bus and are differentiated by their output destinations, number
of Product Terms.
The PLDs consume minimal power by using Zero-Power design techniques. The speed
and power consumption of the PLD is controlled by the Turbo Bit in the PMMR0 register
and other bits in the PMMR2 registers. These registers are set by the microcontroller at
runtime. There is a slight penalty to PLD propagation time when invoking the non-Turbo
bit.
Table 2. PLD I/O Table
Decode PLD
General Purpose PLD
•
•
•
A 1 or 2 Mbit Flash
A secondary 256 Kbit Flash memory
16, 64 or 256 Kbit SRAM.
Name
Abbreviation
DPLD
GPLD
Inputs
57
57
Outputs
15
19
Preliminary Information
Product Terms
114
39