psd935g2 STMicroelectronics, psd935g2 Datasheet - Page 55

• Manufacturer Part Number: psd935g2
• Description: Configurable Memory System On A Chip For 8-bit Microcontrollers
• Manufacturer: STMicroelectronics

The
PSD935G2
Functional
Blocks
(cont.)
54
PSD9XX Family
9.4.8 Port F – Functionality and Structure
Port F can be configured to perform one or more of the following functions:
9.4.9 Port G – Functionality and Structure
Port G can be configured to perform one or more of the following functions:
Figure 23. Ports E, F and G Structure
MCU I/O Mode
PLD Input – as direct input ot the PLD array.
Address In – additional high address inputs. Direct input to the PLD array.
Latched Address Out – Provide latched address out per Table 18.
Slew Rate – pins can be set up for fast slew rate.
Data Port – connected to D[7:0] when Port F is configured as Data Port for a
non-multiplexed bus.
MCU I/O Mode
Latched Address Out – Provide latched address out per Table 18.
Open Drain – pins can be configured in Open Drain Mode
ADDRESS
ALE
WR
WR
WR
CONTROL REG.
DATA OUT
READ MUX
DIR REG.
D
D
G
D
D
REG.
D
B
P
Q
Q
Q
Q
ISP OR BATTERY BACK-UP (PORT E)
A [ 7:0 ] OR A [ 15:8 ]
ADDRESS
DATA OUT
PLD INPUT (PORT F)
DATA IN
OUTPUT
SELECT
OUTPUT
MUX
PSD935G2
CONFIGURATION
BIT
PORT PIN