cym1846p8-35c Cypress Semiconductor Corporation., cym1846p8-35c Datasheet - Page 4

• Manufacturer Part Number: cym1846p8-35c
• Description: 512k X 32 Static Ram Module
• Manufacturer: Cypress Semiconductor Corporation.

Switching Characteristics
READ CYCLE
t
t
t
t
t
t
t
t
t
t
WRITE CYCLE
t
t
t
t
t
t
t
t
t
t
Notes:
RC
AA
OHA
ACS
DOE
LZOE
HZOE
LZCS
HZCS
PD
WC
SCS
AW
HA
SA
PWE
SD
HD
LZWE
HZWE
3.
4.
5.
6.
Parameter
Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
I
At any given temperature and voltage condition, t
t
The internal write time of the memory is defined by the overlap of CS LOW and WE LOW. Both signals must be LOW to initiate a write and either signal can
terminate a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write.
OL
HZCS
/I
OH
and t
and 30-pF load capacitance.
HZWE
[6]
Read Cycle Time
Address to Data Valid
Data Hold from Address Change
CS LOW to Data Valid
OE LOW to Data Valid
OE LOW to Low Z
OE HIGH to High Z
CS LOW to Low Z
CS HIGH to High Z
CS HIGH to Power-Down
Write Cycle Time
CS LOW to Write End
Address Set-Up to Write End
Address Hold from Write End
Address Set-Up to Write Start
WE Pulse Width
Data Set-Up to Write End
Data Hold from Write End
WE HIGH to Low Z
WE LOW to High Z
are specified with C
Description
L
Over the Operating Range
= 5 pF as in part (b) of AC Test Loads and Waveforms. Transition is measured 500 mV from steady-state voltage.
[4]
[6]
[4, 5]
HZCS
is less than t
LZCS
[3]
for any given device. These parameters are guaranteed and not 100% tested.
4
(continued)
Min.
20
20
15
15
15
10
3
0
3
0
1
1
3
0
1846–20
Max.
20
20
10
10
10
20
10
Min.
25
25
20
20
20
15
3
0
3
0
2
2
4
0
1846–25
Max.
25
25
15
12
12
25
12
Min.
35
35
30
30
30
20
3
0
3
0
2
2
5
0
1846–35
Max.
CYM1846
35
35
25
12
12
35
12
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns