k4h281638d Samsung Semiconductor, Inc., k4h281638d Datasheet - Page 41

• Manufacturer Part Number: k4h281638d
• Description: 128mb D-die X16 Ddr Sdram
• Manufacturer: Samsung Semiconductor, Inc.

128Mb D-die(x16) DDR SDRAM
7.3 IDD spec table
< Detailed test conditions for DDR SDRAM IDD1 & IDD7 >
IDD1 : Operating current: One bank operation
1. Typical Case : Vdd = 2.5V, T=25’ C
2. Worst Case : Vdd = 2.7V, T= 10’ C
3. Only one bank is accessed with tRC(min), Burst Mode, Address and Control inputs on NOP edge are changing once
4. Timing patterns
Symbol
Legend : A=Activate, R=Read, W=Write, P=Precharge, N=NOP
- DDR200(100Mhz, CL=2) : tCK = 10ns, CL2, BL=4, tRCD = 2*tCK, tRAS = 5*tCK
- DDR266B(133Mhz, CL=2.5) : tCK = 7.5ns, CL=2.5, BL=4, tRCD = 3*tCK, tRC = 9*tCK, tRAS = 5*tCK
- DDR266A (133Mhz, CL=2) : tCK = 7.5ns, CL=2, BL=4, tRCD = 3*tCK, tRC = 9*tCK, tRAS = 5*tCK
- DDR333(166Mhz, CL=2.5) : tCK=6ns, CL=2.5, BL=4, tRCD=10*tCK, tRAS=7*tCK
per clock cycle. lout = 0mA
*50% of data changing at every burst
*50% of data changing at every burst
*50% of data changing at every burst
IDD6
*50% of data changing at every burst
Read : A0 N N R0 N P0 N N N A0 N - repeat the same timing with random address changing
Read : A0 N N R0 N P0 N N N A0 N - repeat the same timing with random address changing
Read : A0 N N R0 N P0 N N N A0 N - repeat the same timing with random address changing
Read : A0 N R0 N N P0 N A0 N - repeat the same timing with random address changing
IDD4W
IDD2Q
IDD2P
IDD2F
IDD3P
IDD3N
IDD4R
IDD7A
IDD0
IDD1
IDD5
Low power
Normal
K4H281638D-
(DDR333)
Table 12. IDD SPEC Table
TCB3
105
135
190
170
190
345
25
18
35
60
3
2
1
K4H281638D-
(DDR266A)
TCA2
125
172
150
180
320
95
25
18
35
55
3
2
1
K4H281638D-
(DDR266B)
- 41 -
TCB0
125
172
150
180
320
95
25
18
35
55
3
2
1
K4H281638D-
(DDR200)
TCA0
115
150
120
165
255
2.5
85
22
18
28
45
2
1
(V
DD
Unit
=2.7V, T = 10
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
REV. 0.6 Oct. 21. 2002
Optional
Notes
C
)