r8a66171dd Renesas Electronics Corporation., r8a66171dd Datasheet - Page 8

• Manufacturer Part Number: r8a66171dd
• Description: A2rt Advanced Asynchronous Receiver & Transmitter
• Manufacturer: Renesas Electronics Corporation.

R8A66171DD/SP
REJ03F269-0100 Rev.1.00 Feb.19.2008
Page 8 of 22
● Error reset
● Internal reset
● CRC
● Error detection
SUPPLEMENTARY DESCRIPTION
● Parity check
Comparison between parity check and CRC
CRC deals with data characters in transmitted or received blocks. (Start, stop and wakeup bits are
When the CRC is enabled, the transmit and receive data consists of block length (1~64 bytes) + 2 bytes
Parity check needs only one additional bit and is highly efficient. The formula is straightforward, and
includes even parity and odd parity checks. In both cases, one bit is added.
The CRC poly-nominal expression is CRC-CCITT X
excluded.)
(block check characters). The following table shows the comparison between parity check and CRC.
Parity check
(1)Parity error
(2)Framing error
(3)Overrun error
(4)CRC error
When D4 bit of command4 is 1, D3 bit, D4 bit, D5 bit and D6 bit of status1 are reset.
When an error reset pulse occurs, D4 bit of command4 becomes 0.
Again, D4 bit of command4 need not be adjusted to 0.
When D5 bit of command4 becomes 1, all command status information is reset, and the signal based
on reset command status information is output to each output.
When an internal reset pulse occurs, D5 bit of command4 becomes 0.
Again, D5 bit of command4 need not be adjusted to 0.
When a parity error occurs, D5 bit of status1 information is set. The data is send to the receive data
buffer (FIFO).
When a framing error occurs, D3 bit of the status1 information is set. The data is sent to the receive
data buffer (FIFO).
When data is received before all data in the receive data buffer (FIFO) has been read by MCU, D4
bit of the status1 information is set as an overrun error.
In this case, the new data in the receive buffer are lost.
When an error occurs after receiving block check character, D6 bit of the status1 information is set.
The above error information is maintained until D4 bit of command4 is set.
CRC
Burst error is not detected. (50% of which can be detected.)
Burst error can be detected. (Burst error detection rate is more than 99.9%.)
16
+X
12
+X
5
+1.