r8a66161dd Renesas Electronics Corporation., r8a66161dd Datasheet - Page 2

• Manufacturer Part Number: r8a66161dd
• Description: 16-bit Led Driver With Shift Register And Latch
• Manufacturer: Renesas Electronics Corporation.

R8A66161DD/SP
PIN CONFIGURATION ( TOP VIEW )
FUNCTIONAL DESCRIPTION
As R8A66161 uses silicon gate CMOS process. It realizes high-speed and high-output currents sufficient for
LED drive while maintaining low power consumption and allowance for high noises.
Each bit of a shift register consists of two flip-flop having independent clocks for shifting and latching.
As for clock input, shift clock input CK
latch operations being made when “L” changes to “H”.
Serial data input A is the data input of the first-step shift register and the signal of A shifts shifting registers
one by one when a pulse is impressed to CK
When the pulse is impressed to CK
register, and they appear in the parallel data outputs from Q
Outputs Q
To extend the number of bits, use the serial data output SQ
of the 16th bit.
When reset input R is changed to “L”, Q
are set.
If “H” is impressed to output enable input OE, Q
reach the high impedance state. Furthermore, change in OE does not affect shift operation.
FUNCTION TABLE
REJ03F0262-0100 Rev.1.00 Jan.16.2008
page 2 of 7
Shift
Shift
Shift
Latch
Latch
Latch
operation
operation
operation
Note1: ↑
Note1: ↑
Note1: ↑
Operation mode
Operation mode
Operation mode
Output disable
Output disable
Output disable
t
t
t
1
1
1
Reset
Reset
Reset
, t
, t
, t
Z
Z
Z
Q
Q
Q
X
X
X
q
q
q
q
q
q
2
2
2
0
0
0
0
0
0
Shift t
Shift t
Shift t
Latch t
Latch t
Latch t
Shift t
Shift t
Shift t
Latch t
Latch t
Latch t
A
: Change from low-level to high-level
: Change from low-level to high-level
: Change from low-level to high-level
: Output state Q before CK
: Output state Q before CK
: Output state Q before CK
: Irrelevant
: Irrelevant
: Irrelevant
: Contents of shift register before CK
: Contents of shift register before CK
: Contents of shift register before CK
: Contents of shift register
: Contents of shift register
: Contents of shift register
: t
: t
: t
: High impedance
: High impedance
: High impedance
2
2
2
~ Q
PARALLEL DATA
PARALLEL DATA
OUTPUTS
OUTPUTS
SERIAL DATA INPUT
SERIAL DATA INPUT
ENABLE INPUT
ENABLE INPUT
LATCH CLOCK INPUT
LATCH CLOCK INPUT
DIRECT RESET INPUT
DIRECT RESET INPUT
SHIFT CLOCK INPUT
SHIFT CLOCK INPUT
SERIAL DATA OUTPUT
SERIAL DATA OUTPUT
PARALLEL DATA
PARALLEL DATA
OUTPUTS
OUTPUTS
is set after t
is set after t
is set after t
1
1
1
1
1
1
2
2
2
2
2
2
P
are open drain outputs.
R
R
R
L
L
L
H
H
H
H
H
H
H
H
H
H
H
H
X
X
X
CK
CK
CK
↑
↑
↑
↑
↑
↑
X
X
X
X
X
X
X
X
X
X
X
X
1
1
1
S
S
S
is set
is set
is set
Input
Input
Input
CK
CK
CK
↑
↑
↑
↑
↑
↑
X
X
X
X
X
X
X
X
X
X
X
X
L
L
L
(Note: 1)
H
H
H
A
A
A
X
X
X
X
X
X
L
L
L
X
X
X
X
X
X
L
L
L
changed
changed
changed
OE
OE
OE
X
X
X
H
H
H
L
L
L
L
L
L
L
L
L
L
L
L
L
Q
Q
Q
Q
Q
Q
Q
Q
Q
, the contents of the shifting register at that time are stored in a latching
Z
Z
Z
L
L
L
Z
Z
Z
Z
Z
Z
A
A
A
A
A
A
A
A
A
S
0
0
0
0
0
0
S
S
S
Q
Q
Q
Q
Q
Q
V
V
A
A
OE
OE
OE
CK
CK
R
R R
CK
CK
GND
GND
SQ
SQ
Q
Q
Q
Q
Q
Q
changed
changed
changed
and latch clock input CK
CC
CC
A
A
A
A
B
B
B
O
O
O
P
P
P
Q
Q
Q
Q
Q
Q
q
q
q
Q
Q
Q
q
q
q
Z
Z
Z
Z
Z
Z
A 0
A 0
A 0
A 0
A 0
A 0
L
L
S
S
B
B
B
B
B
B
B
B
B
P
P
~ Q
0
0
0
0
0
0
Q
Q
Q
Q
Q
Q
q
q
q
Q
Q
Q
q
q
q
S
Z
Z
Z
Z
Z
Z
B 0
B 0
B 0
B 0
B 0
B 0
C
C
C
C
C
C
C
C
C
. When A is “H”, the signal of “L” shifts.
P
0
0
0
0
0
0
10
10
11
11
12
12
and SQ
Q
Q
Q
Q
Q
Q
q
q
q
Q
Q
Q
q
q
q
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
A
Z
Z
Z
Z
Z
Z
C 0
C 0
C 0
C 0
C 0
C 0
D
D
D
D
D
D
D
D
D
0
0
0
0
0
0
~ Q
Q
Q
Q
q
q
q
Q
Q
Q
q
q
q
Q
Q
Q
Z
Z
Z
Z
Z
Z
D 0
D 0
D 0
D 0
D 0
D 0
E
E
E
E
E
E
E
E
E
QA
QA
QB
QB
A
A
OE
OE
CKL
CKL
R
R
CKS
CKS
SQP
SQP
QO
QO
QP
QP
0
0
0
0
0
0
P
P
reaches the high impedance state, but SQ
Q
Q
Q
q
q
q
Q
Q
Q
q
q
q
Q
Q
Q
Z
Z
Z
Z
Z
Z
E 0
E 0
E 0
E 0
E 0
E 0
F
F
F
F
F
F
F
F
F
are reset. In this case, shifting and latching register
0
0
0
0
0
0
Parallel data output
Parallel data output
Parallel data output
A
Q
Q
Q
Q
Q
Q
Q
Q
Q
q
q
q
q
q
q
P
QC
QC
QD
QD
QE
QE
QF
QF
QG
QG
QH
QH
QI
QI
QJ
QJ
QK
QK
QL
QL
QM
QM
QN
QN
Z
Z
Z
Z
Z
Z
F 0
F 0
F 0
F 0
F 0
F 0
G
G
G
G
G
G
G
G
G
~ Q
0
0
0
0
0
0
which shows the output of the shifting register
Q
Q
Q
q
q
q
Q
Q
Q
q
q
q
Q
Q
Q
Z
Z
Z
Z
Z
Z
L
G 0
G 0
G 0
G 0
G 0
G 0
H
H
H
H
H
H
P
H
H
H
0
0
0
0
0
0
are independent from each other, shift and
.
24
24
23
23
22
22
21
21
20
20
19
19
18
18
17
17
16
16
15
15
14
14
13
13
Q
Q
Q
q
q
q
Q
Q
Q
q
q
q
Q
Q
Q
Z
Z
Z
Z
Z
Z
H 0
H 0
H 0
H 0
H 0
H 0
I
I
I
I
I
I
I
I
I
0
0
0
0
0
0
Q
Q
Q
q
q
q
Q
Q
Q
q
q
q
Q
Q
Q
Z
Z
Z
Z
Z
Z
I 0
I 0
I 0
I 0
I 0
I 0
J
J
J
J
J
J
J
J
J
0
0
0
0
0
0
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
C
C
D
D
E
E
F
F
G
G
H
H
I
I
J
J
K
K
L
L
M
M
N
N
Q
Q
Q
q
q
q
Q
Q
Q
q
q
q
Q
Q
Q
Z
Z
Z
Z
Z
Z
J 0
J 0
J 0
J 0
J 0
J 0
K
K
K
K
K
K
K
K
K
0
0
0
0
0
0
Q
Q
Q
q
q
q
Q
Q
Q
q
q
q
Q
Q
Q
Z
Z
Z
Z
Z
Z
K 0
K 0
K 0
K 0
K 0
K 0
L
L
L
L
L
L
L
L
L
0
0
0
0
0
0
PARALLEL DATA
PARALLEL DATA
OUTPUTS
OUTPUTS
Q
Q
Q
Q
Q
Q
Q
Q
Q
q
q
q
q
q
q
Z
Z
Z
Z
Z
Z
L 0
L 0
L 0
L 0
L 0
L 0
M
M
M
M
M
M
M
M
M
0
0
0
0
0
0
Q
Q
Q
q
q
q
Q
Q
Q
q
q
q
Q
Q
Q
Z
Z
Z
Z
Z
Z
M 0
M 0
M 0
M 0
M 0
M 0
N
N
N
N
N
N
N
N
N
0
0
0
0
0
0
q
q
q
q
q
q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Z
Z
Z
Z
Z
Z
N 0
N 0
N 0
N 0
N 0
N 0
O
O
O
O
O
O
O
O
O
0
0
0
0
0
0
Q
Q
Q
q
q
q
Q
Q
Q
q
q
q
Q
Q
Q
Z
Z
Z
Z q
Z q
Z q
O 0
O 0
O 0
O 0
O 0
O 0
P
P
P
P
P
P
P
P
P
0
0
0
0
0
0
Serial
Serial
Serial
data
data
data
output
output
output
SQ
SQ
SQ
q
q
q
q
q
q
q
q
q
q
q
q
P
L
L
L
O 0
O 0
O 0
O 0
O 0
O 0
O 0
O 0
O 0
O 0
O 0
O 0
P
P
P
P
P
P
does not
Remarks
Remarks
Remarks
Output
Output
Output
Lighting
Lighting
Lighting
Output
Output
Output
Lights-out
Lights-out
Lights-out
H
H
H
L
L
L